[llvm-branch-commits] [llvm-branch] r368421 - Merging r367750:
Hans Wennborg via llvm-branch-commits
llvm-branch-commits at lists.llvm.org
Fri Aug 9 02:45:06 PDT 2019
Author: hans
Date: Fri Aug 9 02:45:06 2019
New Revision: 368421
URL: http://llvm.org/viewvc/llvm-project?rev=368421&view=rev
Log:
Merging r367750:
------------------------------------------------------------------------
r367750 | void | 2019-08-03 07:52:47 +0200 (Sat, 03 Aug 2019) | 15 lines
Emit diagnostic if an inline asm constraint requires an immediate
Summary:
An inline asm call can result in an immediate after inlining. Therefore emit a
diagnostic here if constraint requires an immediate but one isn't supplied.
Reviewers: joerg, mgorny, efriedma, rsmith
Reviewed By: joerg
Subscribers: asb, rbar, johnrusso, simoncook, apazos, sabuasal, niosHD, zzheng, edward-jones, rogfer01, MartinMosbeck, brucehoult, the_o, PkmX, jocewei, s.egerton, MaskRay, jyknight, dylanmckay, javed.absar, fedor.sergeev, jrtc27, Jim, krytarowski, eraman, llvm-commits
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D60942
------------------------------------------------------------------------
Added:
llvm/branches/release_90/test/CodeGen/X86/inline-asm-e-constraint.ll
- copied unchanged from r367750, llvm/trunk/test/CodeGen/X86/inline-asm-e-constraint.ll
llvm/branches/release_90/test/CodeGen/X86/inline-asm-imm-out-of-range.ll
- copied unchanged from r367750, llvm/trunk/test/CodeGen/X86/inline-asm-imm-out-of-range.ll
llvm/branches/release_90/test/CodeGen/X86/inline-asm-n-constraint.ll
- copied unchanged from r367750, llvm/trunk/test/CodeGen/X86/inline-asm-n-constraint.ll
Modified:
llvm/branches/release_90/ (props changed)
llvm/branches/release_90/include/llvm/CodeGen/TargetLowering.h
llvm/branches/release_90/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
llvm/branches/release_90/lib/CodeGen/SelectionDAG/TargetLowering.cpp
llvm/branches/release_90/lib/Target/AArch64/AArch64ISelLowering.cpp
llvm/branches/release_90/lib/Target/ARM/ARMISelLowering.cpp
llvm/branches/release_90/lib/Target/AVR/AVRISelLowering.cpp
llvm/branches/release_90/lib/Target/RISCV/RISCVISelLowering.cpp
llvm/branches/release_90/lib/Target/Sparc/SparcISelLowering.cpp
llvm/branches/release_90/lib/Target/SystemZ/SystemZISelLowering.cpp
llvm/branches/release_90/lib/Target/X86/X86ISelLowering.cpp
llvm/branches/release_90/test/CodeGen/AArch64/arm64-inline-asm-error-I.ll
llvm/branches/release_90/test/CodeGen/AArch64/arm64-inline-asm-error-J.ll
llvm/branches/release_90/test/CodeGen/AArch64/arm64-inline-asm-error-K.ll
llvm/branches/release_90/test/CodeGen/AArch64/arm64-inline-asm-error-L.ll
llvm/branches/release_90/test/CodeGen/AArch64/arm64-inline-asm-error-M.ll
llvm/branches/release_90/test/CodeGen/AArch64/arm64-inline-asm-error-N.ll
llvm/branches/release_90/test/CodeGen/RISCV/inline-asm-invalid.ll
llvm/branches/release_90/test/CodeGen/X86/inline-asm-bad-constraint-n.ll
Propchange: llvm/branches/release_90/
------------------------------------------------------------------------------
--- svn:mergeinfo (original)
+++ svn:mergeinfo Fri Aug 9 02:45:06 2019
@@ -1,3 +1,3 @@
/llvm/branches/Apple/Pertwee:110850,110961
/llvm/branches/type-system-rewrite:133420-134817
-/llvm/trunk:155241,366431,366481,366487,366527,366570,366660,366868,366925,367030,367062,367124,367215,367292,367304,367306,367314,367340-367341,367394,367396,367398,367403,367417,367662,367753,367846-367847,367898,367941,368004,368315
+/llvm/trunk:155241,366431,366481,366487,366527,366570,366660,366868,366925,367030,367062,367124,367215,367292,367304,367306,367314,367340-367341,367394,367396,367398,367403,367417,367662,367750,367753,367846-367847,367898,367941,368004,368315
Modified: llvm/branches/release_90/include/llvm/CodeGen/TargetLowering.h
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/release_90/include/llvm/CodeGen/TargetLowering.h?rev=368421&r1=368420&r2=368421&view=diff
==============================================================================
--- llvm/branches/release_90/include/llvm/CodeGen/TargetLowering.h (original)
+++ llvm/branches/release_90/include/llvm/CodeGen/TargetLowering.h Fri Aug 9 02:45:06 2019
@@ -3665,6 +3665,7 @@ public:
C_Register, // Constraint represents specific register(s).
C_RegisterClass, // Constraint represents any of register(s) in class.
C_Memory, // Memory constraint.
+ C_Immediate, // Requires an immediate.
C_Other, // Something else.
C_Unknown // Unsupported constraint.
};
Modified: llvm/branches/release_90/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/release_90/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp?rev=368421&r1=368420&r2=368421&view=diff
==============================================================================
--- llvm/branches/release_90/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp (original)
+++ llvm/branches/release_90/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp Fri Aug 9 02:45:06 2019
@@ -8021,6 +8021,14 @@ void SelectionDAGBuilder::visitInlineAsm
// Compute the constraint code and ConstraintType to use.
TLI.ComputeConstraintToUse(T, SDValue());
+ if (T.ConstraintType == TargetLowering::C_Immediate &&
+ OpInfo.CallOperand && !isa<ConstantSDNode>(OpInfo.CallOperand))
+ // We've delayed emitting a diagnostic like the "n" constraint because
+ // inlining could cause an integer showing up.
+ return emitInlineAsmError(
+ CS, "constraint '" + Twine(T.ConstraintCode) + "' expects an "
+ "integer constant expression");
+
ExtraInfo.update(T);
}
@@ -8105,7 +8113,8 @@ void SelectionDAGBuilder::visitInlineAsm
switch (OpInfo.Type) {
case InlineAsm::isOutput:
if (OpInfo.ConstraintType == TargetLowering::C_Memory ||
- (OpInfo.ConstraintType == TargetLowering::C_Other &&
+ ((OpInfo.ConstraintType == TargetLowering::C_Immediate ||
+ OpInfo.ConstraintType == TargetLowering::C_Other) &&
OpInfo.isIndirect)) {
unsigned ConstraintID =
TLI.getInlineAsmMemConstraint(OpInfo.ConstraintCode);
@@ -8119,13 +8128,14 @@ void SelectionDAGBuilder::visitInlineAsm
MVT::i32));
AsmNodeOperands.push_back(OpInfo.CallOperand);
break;
- } else if ((OpInfo.ConstraintType == TargetLowering::C_Other &&
+ } else if (((OpInfo.ConstraintType == TargetLowering::C_Immediate ||
+ OpInfo.ConstraintType == TargetLowering::C_Other) &&
!OpInfo.isIndirect) ||
OpInfo.ConstraintType == TargetLowering::C_Register ||
OpInfo.ConstraintType == TargetLowering::C_RegisterClass) {
// Otherwise, this outputs to a register (directly for C_Register /
- // C_RegisterClass, and a target-defined fashion for C_Other). Find a
- // register that we can use.
+ // C_RegisterClass, and a target-defined fashion for
+ // C_Immediate/C_Other). Find a register that we can use.
if (OpInfo.AssignedRegs.Regs.empty()) {
emitInlineAsmError(
CS, "couldn't allocate output register for constraint '" +
@@ -8205,15 +8215,24 @@ void SelectionDAGBuilder::visitInlineAsm
}
// Treat indirect 'X' constraint as memory.
- if (OpInfo.ConstraintType == TargetLowering::C_Other &&
+ if ((OpInfo.ConstraintType == TargetLowering::C_Immediate ||
+ OpInfo.ConstraintType == TargetLowering::C_Other) &&
OpInfo.isIndirect)
OpInfo.ConstraintType = TargetLowering::C_Memory;
- if (OpInfo.ConstraintType == TargetLowering::C_Other) {
+ if (OpInfo.ConstraintType == TargetLowering::C_Immediate ||
+ OpInfo.ConstraintType == TargetLowering::C_Other) {
std::vector<SDValue> Ops;
TLI.LowerAsmOperandForConstraint(InOperandVal, OpInfo.ConstraintCode,
Ops, DAG);
if (Ops.empty()) {
+ if (OpInfo.ConstraintType == TargetLowering::C_Immediate)
+ if (isa<ConstantSDNode>(InOperandVal)) {
+ emitInlineAsmError(CS, "value out of range for constraint '" +
+ Twine(OpInfo.ConstraintCode) + "'");
+ return;
+ }
+
emitInlineAsmError(CS, "invalid operand for inline asm constraint '" +
Twine(OpInfo.ConstraintCode) + "'");
return;
@@ -8250,7 +8269,8 @@ void SelectionDAGBuilder::visitInlineAsm
}
assert((OpInfo.ConstraintType == TargetLowering::C_RegisterClass ||
- OpInfo.ConstraintType == TargetLowering::C_Register) &&
+ OpInfo.ConstraintType == TargetLowering::C_Register ||
+ OpInfo.ConstraintType == TargetLowering::C_Immediate) &&
"Unknown constraint type!");
// TODO: Support this.
@@ -8356,6 +8376,7 @@ void SelectionDAGBuilder::visitInlineAsm
Val = OpInfo.AssignedRegs.getCopyFromRegs(
DAG, FuncInfo, getCurSDLoc(), Chain, &Flag, CS.getInstruction());
break;
+ case TargetLowering::C_Immediate:
case TargetLowering::C_Other:
Val = TLI.LowerAsmOutputForConstraint(Chain, Flag, getCurSDLoc(),
OpInfo, DAG);
Modified: llvm/branches/release_90/lib/CodeGen/SelectionDAG/TargetLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/release_90/lib/CodeGen/SelectionDAG/TargetLowering.cpp?rev=368421&r1=368420&r2=368421&view=diff
==============================================================================
--- llvm/branches/release_90/lib/CodeGen/SelectionDAG/TargetLowering.cpp (original)
+++ llvm/branches/release_90/lib/CodeGen/SelectionDAG/TargetLowering.cpp Fri Aug 9 02:45:06 2019
@@ -3567,15 +3567,17 @@ TargetLowering::getConstraintType(String
if (S == 1) {
switch (Constraint[0]) {
default: break;
- case 'r': return C_RegisterClass;
+ case 'r':
+ return C_RegisterClass;
case 'm': // memory
case 'o': // offsetable
case 'V': // not offsetable
return C_Memory;
- case 'i': // Simple Integer or Relocatable Constant
case 'n': // Simple Integer
case 'E': // Floating Point Constant
case 'F': // Floating Point Constant
+ return C_Immediate;
+ case 'i': // Simple Integer or Relocatable Constant
case 's': // Relocatable Constant
case 'p': // Address.
case 'X': // Allow ANY value.
@@ -3950,6 +3952,7 @@ TargetLowering::ParseConstraints(const D
/// Return an integer indicating how general CT is.
static unsigned getConstraintGenerality(TargetLowering::ConstraintType CT) {
switch (CT) {
+ case TargetLowering::C_Immediate:
case TargetLowering::C_Other:
case TargetLowering::C_Unknown:
return 0;
@@ -4069,11 +4072,12 @@ static void ChooseConstraint(TargetLower
TargetLowering::ConstraintType CType =
TLI.getConstraintType(OpInfo.Codes[i]);
- // If this is an 'other' constraint, see if the operand is valid for it.
- // For example, on X86 we might have an 'rI' constraint. If the operand
- // is an integer in the range [0..31] we want to use I (saving a load
- // of a register), otherwise we must use 'r'.
- if (CType == TargetLowering::C_Other && Op.getNode()) {
+ // If this is an 'other' or 'immediate' constraint, see if the operand is
+ // valid for it. For example, on X86 we might have an 'rI' constraint. If
+ // the operand is an integer in the range [0..31] we want to use I (saving a
+ // load of a register), otherwise we must use 'r'.
+ if ((CType == TargetLowering::C_Other ||
+ CType == TargetLowering::C_Immediate) && Op.getNode()) {
assert(OpInfo.Codes[i].size() == 1 &&
"Unhandled multi-letter 'other' constraint");
std::vector<SDValue> ResultOps;
Modified: llvm/branches/release_90/lib/Target/AArch64/AArch64ISelLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/release_90/lib/Target/AArch64/AArch64ISelLowering.cpp?rev=368421&r1=368420&r2=368421&view=diff
==============================================================================
--- llvm/branches/release_90/lib/Target/AArch64/AArch64ISelLowering.cpp (original)
+++ llvm/branches/release_90/lib/Target/AArch64/AArch64ISelLowering.cpp Fri Aug 9 02:45:06 2019
@@ -5665,8 +5665,6 @@ AArch64TargetLowering::getConstraintType
switch (Constraint[0]) {
default:
break;
- case 'z':
- return C_Other;
case 'x':
case 'w':
return C_RegisterClass;
@@ -5674,6 +5672,16 @@ AArch64TargetLowering::getConstraintType
// currently handle addresses it is the same as 'r'.
case 'Q':
return C_Memory;
+ case 'I':
+ case 'J':
+ case 'K':
+ case 'L':
+ case 'M':
+ case 'N':
+ case 'Y':
+ case 'Z':
+ return C_Immediate;
+ case 'z':
case 'S': // A symbolic address
return C_Other;
}
Modified: llvm/branches/release_90/lib/Target/ARM/ARMISelLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/release_90/lib/Target/ARM/ARMISelLowering.cpp?rev=368421&r1=368420&r2=368421&view=diff
==============================================================================
--- llvm/branches/release_90/lib/Target/ARM/ARMISelLowering.cpp (original)
+++ llvm/branches/release_90/lib/Target/ARM/ARMISelLowering.cpp Fri Aug 9 02:45:06 2019
@@ -14369,7 +14369,8 @@ const char *ARMTargetLowering::LowerXCon
/// constraint it is for this target.
ARMTargetLowering::ConstraintType
ARMTargetLowering::getConstraintType(StringRef Constraint) const {
- if (Constraint.size() == 1) {
+ unsigned S = Constraint.size();
+ if (S == 1) {
switch (Constraint[0]) {
default: break;
case 'l': return C_RegisterClass;
@@ -14377,12 +14378,12 @@ ARMTargetLowering::getConstraintType(Str
case 'h': return C_RegisterClass;
case 'x': return C_RegisterClass;
case 't': return C_RegisterClass;
- case 'j': return C_Other; // Constant for movw.
- // An address with a single base register. Due to the way we
- // currently handle addresses it is the same as an 'r' memory constraint.
+ case 'j': return C_Immediate; // Constant for movw.
+ // An address with a single base register. Due to the way we
+ // currently handle addresses it is the same as an 'r' memory constraint.
case 'Q': return C_Memory;
}
- } else if (Constraint.size() == 2) {
+ } else if (S == 2) {
switch (Constraint[0]) {
default: break;
case 'T': return C_RegisterClass;
Modified: llvm/branches/release_90/lib/Target/AVR/AVRISelLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/release_90/lib/Target/AVR/AVRISelLowering.cpp?rev=368421&r1=368420&r2=368421&view=diff
==============================================================================
--- llvm/branches/release_90/lib/Target/AVR/AVRISelLowering.cpp (original)
+++ llvm/branches/release_90/lib/Target/AVR/AVRISelLowering.cpp Fri Aug 9 02:45:06 2019
@@ -1689,6 +1689,8 @@ AVRTargetLowering::getConstraintType(Str
if (Constraint.size() == 1) {
// See http://www.nongnu.org/avr-libc/user-manual/inline_asm.html
switch (Constraint[0]) {
+ default:
+ break;
case 'a': // Simple upper registers
case 'b': // Base pointer registers pairs
case 'd': // Upper register
@@ -1715,9 +1717,7 @@ AVRTargetLowering::getConstraintType(Str
case 'O': // Integer constant (Range: 8, 16, 24)
case 'P': // Integer constant (Range: 1)
case 'R': // Integer constant (Range: -6 to 5)x
- return C_Other;
- default:
- break;
+ return C_Immediate;
}
}
Modified: llvm/branches/release_90/lib/Target/RISCV/RISCVISelLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/release_90/lib/Target/RISCV/RISCVISelLowering.cpp?rev=368421&r1=368420&r2=368421&view=diff
==============================================================================
--- llvm/branches/release_90/lib/Target/RISCV/RISCVISelLowering.cpp (original)
+++ llvm/branches/release_90/lib/Target/RISCV/RISCVISelLowering.cpp Fri Aug 9 02:45:06 2019
@@ -2407,6 +2407,10 @@ RISCVTargetLowering::getConstraintType(S
break;
case 'f':
return C_RegisterClass;
+ case 'I':
+ case 'J':
+ case 'K':
+ return C_Immediate;
}
}
return TargetLowering::getConstraintType(Constraint);
Modified: llvm/branches/release_90/lib/Target/Sparc/SparcISelLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/release_90/lib/Target/Sparc/SparcISelLowering.cpp?rev=368421&r1=368420&r2=368421&view=diff
==============================================================================
--- llvm/branches/release_90/lib/Target/Sparc/SparcISelLowering.cpp (original)
+++ llvm/branches/release_90/lib/Target/Sparc/SparcISelLowering.cpp Fri Aug 9 02:45:06 2019
@@ -3183,7 +3183,7 @@ SparcTargetLowering::getConstraintType(S
case 'e':
return C_RegisterClass;
case 'I': // SIMM13
- return C_Other;
+ return C_Immediate;
}
}
Modified: llvm/branches/release_90/lib/Target/SystemZ/SystemZISelLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/release_90/lib/Target/SystemZ/SystemZISelLowering.cpp?rev=368421&r1=368420&r2=368421&view=diff
==============================================================================
--- llvm/branches/release_90/lib/Target/SystemZ/SystemZISelLowering.cpp (original)
+++ llvm/branches/release_90/lib/Target/SystemZ/SystemZISelLowering.cpp Fri Aug 9 02:45:06 2019
@@ -956,7 +956,7 @@ SystemZTargetLowering::getConstraintType
case 'K': // Signed 16-bit constant
case 'L': // Signed 20-bit displacement (on all targets we support)
case 'M': // 0x7fffffff
- return C_Other;
+ return C_Immediate;
default:
break;
Modified: llvm/branches/release_90/lib/Target/X86/X86ISelLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/release_90/lib/Target/X86/X86ISelLowering.cpp?rev=368421&r1=368420&r2=368421&view=diff
==============================================================================
--- llvm/branches/release_90/lib/Target/X86/X86ISelLowering.cpp (original)
+++ llvm/branches/release_90/lib/Target/X86/X86ISelLowering.cpp Fri Aug 9 02:45:06 2019
@@ -44656,10 +44656,11 @@ X86TargetLowering::getConstraintType(Str
case 'I':
case 'J':
case 'K':
- case 'L':
- case 'M':
case 'N':
case 'G':
+ case 'L':
+ case 'M':
+ return C_Immediate;
case 'C':
case 'e':
case 'Z':
Modified: llvm/branches/release_90/test/CodeGen/AArch64/arm64-inline-asm-error-I.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/release_90/test/CodeGen/AArch64/arm64-inline-asm-error-I.ll?rev=368421&r1=368420&r2=368421&view=diff
==============================================================================
--- llvm/branches/release_90/test/CodeGen/AArch64/arm64-inline-asm-error-I.ll (original)
+++ llvm/branches/release_90/test/CodeGen/AArch64/arm64-inline-asm-error-I.ll Fri Aug 9 02:45:06 2019
@@ -2,7 +2,7 @@
; RUN: FileCheck --check-prefix=CHECK-ERRORS < %t %s
; Check for at least one invalid constant.
-; CHECK-ERRORS: error: invalid operand for inline asm constraint 'I'
+; CHECK-ERRORS: error: value out of range for constraint 'I'
define i32 @constraint_I(i32 %i, i32 %j) nounwind ssp {
entry:
Modified: llvm/branches/release_90/test/CodeGen/AArch64/arm64-inline-asm-error-J.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/release_90/test/CodeGen/AArch64/arm64-inline-asm-error-J.ll?rev=368421&r1=368420&r2=368421&view=diff
==============================================================================
--- llvm/branches/release_90/test/CodeGen/AArch64/arm64-inline-asm-error-J.ll (original)
+++ llvm/branches/release_90/test/CodeGen/AArch64/arm64-inline-asm-error-J.ll Fri Aug 9 02:45:06 2019
@@ -2,7 +2,7 @@
; RUN: FileCheck --check-prefix=CHECK-ERRORS < %t %s
; Check for at least one invalid constant.
-; CHECK-ERRORS: error: invalid operand for inline asm constraint 'J'
+; CHECK-ERRORS: error: value out of range for constraint 'J'
define i32 @constraint_J(i32 %i, i32 %j) nounwind ssp {
entry:
Modified: llvm/branches/release_90/test/CodeGen/AArch64/arm64-inline-asm-error-K.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/release_90/test/CodeGen/AArch64/arm64-inline-asm-error-K.ll?rev=368421&r1=368420&r2=368421&view=diff
==============================================================================
--- llvm/branches/release_90/test/CodeGen/AArch64/arm64-inline-asm-error-K.ll (original)
+++ llvm/branches/release_90/test/CodeGen/AArch64/arm64-inline-asm-error-K.ll Fri Aug 9 02:45:06 2019
@@ -2,7 +2,7 @@
; RUN: FileCheck --check-prefix=CHECK-ERRORS < %t %s
; Check for at least one invalid constant.
-; CHECK-ERRORS: error: invalid operand for inline asm constraint 'K'
+; CHECK-ERRORS: error: value out of range for constraint 'K'
define i32 @constraint_K(i32 %i, i32 %j) nounwind {
entry:
Modified: llvm/branches/release_90/test/CodeGen/AArch64/arm64-inline-asm-error-L.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/release_90/test/CodeGen/AArch64/arm64-inline-asm-error-L.ll?rev=368421&r1=368420&r2=368421&view=diff
==============================================================================
--- llvm/branches/release_90/test/CodeGen/AArch64/arm64-inline-asm-error-L.ll (original)
+++ llvm/branches/release_90/test/CodeGen/AArch64/arm64-inline-asm-error-L.ll Fri Aug 9 02:45:06 2019
@@ -2,7 +2,7 @@
; RUN: FileCheck --check-prefix=CHECK-ERRORS < %t %s
; Check for at least one invalid constant.
-; CHECK-ERRORS: error: invalid operand for inline asm constraint 'L'
+; CHECK-ERRORS: error: value out of range for constraint 'L'
define i32 @constraint_L(i32 %i, i32 %j) nounwind {
entry:
Modified: llvm/branches/release_90/test/CodeGen/AArch64/arm64-inline-asm-error-M.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/release_90/test/CodeGen/AArch64/arm64-inline-asm-error-M.ll?rev=368421&r1=368420&r2=368421&view=diff
==============================================================================
--- llvm/branches/release_90/test/CodeGen/AArch64/arm64-inline-asm-error-M.ll (original)
+++ llvm/branches/release_90/test/CodeGen/AArch64/arm64-inline-asm-error-M.ll Fri Aug 9 02:45:06 2019
@@ -2,7 +2,7 @@
; RUN: FileCheck --check-prefix=CHECK-ERRORS < %t %s
; Check for at least one invalid constant.
-; CHECK-ERRORS: error: invalid operand for inline asm constraint 'M'
+; CHECK-ERRORS: error: value out of range for constraint 'M'
define i32 @constraint_M(i32 %i, i32 %j) nounwind {
entry:
Modified: llvm/branches/release_90/test/CodeGen/AArch64/arm64-inline-asm-error-N.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/release_90/test/CodeGen/AArch64/arm64-inline-asm-error-N.ll?rev=368421&r1=368420&r2=368421&view=diff
==============================================================================
--- llvm/branches/release_90/test/CodeGen/AArch64/arm64-inline-asm-error-N.ll (original)
+++ llvm/branches/release_90/test/CodeGen/AArch64/arm64-inline-asm-error-N.ll Fri Aug 9 02:45:06 2019
@@ -2,7 +2,7 @@
; RUN: FileCheck --check-prefix=CHECK-ERRORS < %t %s
; Check for at least one invalid constant.
-; CHECK-ERRORS: error: invalid operand for inline asm constraint 'N'
+; CHECK-ERRORS: error: value out of range for constraint 'N'
define i32 @constraint_N(i32 %i, i32 %j) nounwind {
entry:
Modified: llvm/branches/release_90/test/CodeGen/RISCV/inline-asm-invalid.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/release_90/test/CodeGen/RISCV/inline-asm-invalid.ll?rev=368421&r1=368420&r2=368421&view=diff
==============================================================================
--- llvm/branches/release_90/test/CodeGen/RISCV/inline-asm-invalid.ll (original)
+++ llvm/branches/release_90/test/CodeGen/RISCV/inline-asm-invalid.ll Fri Aug 9 02:45:06 2019
@@ -2,23 +2,23 @@
; RUN: not llc -mtriple=riscv64 < %s 2>&1 | FileCheck %s
define void @constraint_I() {
-; CHECK: error: invalid operand for inline asm constraint 'I'
+; CHECK: error: value out of range for constraint 'I'
tail call void asm sideeffect "addi a0, a0, $0", "I"(i32 2048)
-; CHECK: error: invalid operand for inline asm constraint 'I'
+; CHECK: error: value out of range for constraint 'I'
tail call void asm sideeffect "addi a0, a0, $0", "I"(i32 -2049)
ret void
}
define void @constraint_J() {
-; CHECK: error: invalid operand for inline asm constraint 'J'
+; CHECK: error: value out of range for constraint 'J'
tail call void asm sideeffect "addi a0, a0, $0", "J"(i32 1)
ret void
}
define void @constraint_K() {
-; CHECK: error: invalid operand for inline asm constraint 'K'
+; CHECK: error: value out of range for constraint 'K'
tail call void asm sideeffect "csrwi mstatus, $0", "K"(i32 32)
-; CHECK: error: invalid operand for inline asm constraint 'K'
+; CHECK: error: value out of range for constraint 'K'
tail call void asm sideeffect "csrwi mstatus, $0", "K"(i32 -1)
ret void
}
Modified: llvm/branches/release_90/test/CodeGen/X86/inline-asm-bad-constraint-n.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/release_90/test/CodeGen/X86/inline-asm-bad-constraint-n.ll?rev=368421&r1=368420&r2=368421&view=diff
==============================================================================
--- llvm/branches/release_90/test/CodeGen/X86/inline-asm-bad-constraint-n.ll (original)
+++ llvm/branches/release_90/test/CodeGen/X86/inline-asm-bad-constraint-n.ll Fri Aug 9 02:45:06 2019
@@ -2,7 +2,7 @@
@x = global i32 0, align 4
-;CHECK: error: invalid operand for inline asm constraint 'n'
+; CHECK: error: constraint 'n' expects an integer constant expression
define void @foo() {
%a = getelementptr i32, i32* @x, i32 1
call void asm sideeffect "foo $0", "n"(i32* %a) nounwind
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