[llvm-branch-commits] [llvm-branch] r368419 - Merging r367403:

[Hans Wennborg via llvm-branch-commits]

Author: hans
Date: Fri Aug  9 02:39:44 2019
New Revision: 368419

URL: http://llvm.org/viewvc/llvm-project?rev=368419&view=rev
Log:
Merging r367403:
------------------------------------------------------------------------
r367403 | lenary | 2019-07-31 11:45:55 +0200 (Wed, 31 Jul 2019) | 20 lines

[RISCV] Support 'f' Inline Assembly Constraint

Summary:
This adds the 'f' inline assembly constraint, as supported by GCC. An
'f'-constrained operand is passed in a floating point register. Exactly
which kind of floating-point register (32-bit or 64-bit) is decided
based on the operand type and the available standard extensions (-f and
-d, respectively).

This patch adds support in both the clang frontend, and LLVM itself.

Reviewers: asb, lewis-revill

Reviewed By: asb

Subscribers: hiraditya, rbar, johnrusso, simoncook, apazos, sabuasal, niosHD, kito-cheng, shiva0217, jrtc27, MaskRay, zzheng, edward-jones, rogfer01, MartinMosbeck, brucehoult, the_o, rkruppe, PkmX, jocewei, psnobl, benna, Jim, s.egerton, cfe-commits, llvm-commits

Tags: #clang, #llvm

Differential Revision: https://reviews.llvm.org/D65500
------------------------------------------------------------------------

Added:
    llvm/branches/release_90/test/CodeGen/RISCV/inline-asm-d-constraint-f.ll
      - copied unchanged from r367403, llvm/trunk/test/CodeGen/RISCV/inline-asm-d-constraint-f.ll
    llvm/branches/release_90/test/CodeGen/RISCV/inline-asm-f-constraint-f.ll
      - copied unchanged from r367403, llvm/trunk/test/CodeGen/RISCV/inline-asm-f-constraint-f.ll
Modified:
    llvm/branches/release_90/   (props changed)
    llvm/branches/release_90/lib/Target/RISCV/RISCVISelLowering.cpp
    llvm/branches/release_90/lib/Target/RISCV/RISCVISelLowering.h
    llvm/branches/release_90/test/CodeGen/RISCV/inline-asm-invalid.ll

Propchange: llvm/branches/release_90/
------------------------------------------------------------------------------
--- svn:mergeinfo (original)
+++ svn:mergeinfo Fri Aug  9 02:39:44 2019
@@ -1,3 +1,3 @@
 /llvm/branches/Apple/Pertwee:110850,110961
 /llvm/branches/type-system-rewrite:133420-134817
-/llvm/trunk:155241,366431,366481,366487,366527,366570,366660,366868,366925,367030,367062,367124,367215,367292,367304,367306,367314,367340-367341,367394,367396,367398,367417,367662,367753,367846-367847,367898,367941,368004,368315
+/llvm/trunk:155241,366431,366481,366487,366527,366570,366660,366868,366925,367030,367062,367124,367215,367292,367304,367306,367314,367340-367341,367394,367396,367398,367403,367417,367662,367753,367846-367847,367898,367941,368004,368315

Modified: llvm/branches/release_90/lib/Target/RISCV/RISCVISelLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/release_90/lib/Target/RISCV/RISCVISelLowering.cpp?rev=368419&r1=368418&r2=368419&view=diff
==============================================================================
--- llvm/branches/release_90/lib/Target/RISCV/RISCVISelLowering.cpp (original)
+++ llvm/branches/release_90/lib/Target/RISCV/RISCVISelLowering.cpp Fri Aug  9 02:39:44 2019
@@ -2397,6 +2397,21 @@ const char *RISCVTargetLowering::getTarg
   return nullptr;
 }
 
+/// getConstraintType - Given a constraint letter, return the type of
+/// constraint it is for this target.
+RISCVTargetLowering::ConstraintType
+RISCVTargetLowering::getConstraintType(StringRef Constraint) const {
+  if (Constraint.size() == 1) {
+    switch (Constraint[0]) {
+    default:
+      break;
+    case 'f':
+      return C_RegisterClass;
+    }
+  }
+  return TargetLowering::getConstraintType(Constraint);
+}
+
 std::pair<unsigned, const TargetRegisterClass *>
 RISCVTargetLowering::getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI,
                                                   StringRef Constraint,
@@ -2407,6 +2422,12 @@ RISCVTargetLowering::getRegForInlineAsmC
     switch (Constraint[0]) {
     case 'r':
       return std::make_pair(0U, &RISCV::GPRRegClass);
+    case 'f':
+      if (Subtarget.hasStdExtF() && VT == MVT::f32)
+        return std::make_pair(0U, &RISCV::FPR32RegClass);
+      if (Subtarget.hasStdExtD() && VT == MVT::f64)
+        return std::make_pair(0U, &RISCV::FPR64RegClass);
+      break;
     default:
       break;
     }

Modified: llvm/branches/release_90/lib/Target/RISCV/RISCVISelLowering.h
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/release_90/lib/Target/RISCV/RISCVISelLowering.h?rev=368419&r1=368418&r2=368419&view=diff
==============================================================================
--- llvm/branches/release_90/lib/Target/RISCV/RISCVISelLowering.h (original)
+++ llvm/branches/release_90/lib/Target/RISCV/RISCVISelLowering.h Fri Aug  9 02:39:44 2019
@@ -92,6 +92,7 @@ public:
   // This method returns the name of a target specific DAG node.
   const char *getTargetNodeName(unsigned Opcode) const override;
 
+  ConstraintType getConstraintType(StringRef Constraint) const override;
   std::pair<unsigned, const TargetRegisterClass *>
   getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI,
                                StringRef Constraint, MVT VT) const override;

Modified: llvm/branches/release_90/test/CodeGen/RISCV/inline-asm-invalid.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/release_90/test/CodeGen/RISCV/inline-asm-invalid.ll?rev=368419&r1=368418&r2=368419&view=diff
==============================================================================
--- llvm/branches/release_90/test/CodeGen/RISCV/inline-asm-invalid.ll (original)
+++ llvm/branches/release_90/test/CodeGen/RISCV/inline-asm-invalid.ll Fri Aug  9 02:39:44 2019
@@ -22,3 +22,11 @@ define void @constraint_K() {
   tail call void asm sideeffect "csrwi mstatus, $0", "K"(i32 -1)
   ret void
 }
+
+define void @constraint_f() nounwind {
+; CHECK: error: couldn't allocate input reg for constraint 'f'
+  tail call void asm "fadd.s fa0, fa0, $0", "f"(float 0.0)
+; CHECK: error: couldn't allocate input reg for constraint 'f'
+  tail call void asm "fadd.d fa0, fa0, $0", "f"(double 0.0)
+  ret void
+}