[llvm-dev] Register Number

[Sky Flyer via llvm-dev]

Hi Krzysztof,

Thanks for your reply. I wanted to assign the hardware encoding to the
Instruction bits like the link below:

https://groups.google.com/d/msg/llvm-dev/BfUmfIWYRM8/6JGXQf1gCQAJ

but, at the end, what is assigned to the Inst is, I suppose, the register
ID not the encoding!

to be more clear, I do the followings:
*def D0   : TestReg<0x01,  "d0">,  DwarfRegNum<[0]>;*

and then in InstInfo.td

*bits<6> Dr;let Inst{5-3} = Dr{2-0};*

assuming D0 is passed to $Dr, what I get in the encoding is 110, which I
think is the bit 0 to 2 of what is the returned value in the
TestGenAsmMatcher.inc.
I mean, at the end, Inst{5-3} is getting a value which is not 001.
What am I doing wrong?






On Thu, Sep 17, 2015 at 3:05 PM, Krzysztof Parzyszek via llvm-dev <
llvm-dev at lists.llvm.org> wrote:

> On 9/17/2015 7:04 AM, Sky Flyer via llvm-dev wrote:
>
>> It seems like d0 is always 14!
>> I check it with ARMGenAsmMatcher.inc it was the same!
>> How is it possible? because it should give the same register value that
>> matches the underlying platform not any autogenerated value!?
>>
>
> The returned number is the register id as defined in
> <YourTarget>GenRegisterInfo.inc.  These numbers don't have any meaning
> other than to represent a particular register.  The 0x01 would be the
> encoding used in generating the binary.
>
> The D0 has id 14 on ARM because there are 13 other registers preceding it:
> namespace ARM {
> enum {
>   NoRegister,
>   APSR = 1,
>   APSR_NZCV = 2,
>   CPSR = 3,
>   FPEXC = 4,
>   FPINST = 5,
>   FPSCR = 6,
>   FPSCR_NZCV = 7,
>   FPSID = 8,
>   ITSTATE = 9,
>   LR = 10,
>   PC = 11,
>   SP = 12,
>   SPSR = 13,
>   D0 = 14,
>   ...
>
> -Krzysztof
>
> --
> Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, hosted
> by The Linux Foundation
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