[llvm-dev] Register Number

[Krzysztof Parzyszek via llvm-dev]

On 9/17/2015 8:30 AM, Sky Flyer wrote:
> Hi Krzysztof,
>
> Thanks for your reply. I wanted to assign the hardware encoding to the
> Instruction bits like the link below:
>
> https://groups.google.com/d/msg/llvm-dev/BfUmfIWYRM8/6JGXQf1gCQAJ
>
> but, at the end, what is assigned to the Inst is, I suppose, the
> register ID not the encoding!
>
> to be more clear, I do the followings:
> *def D0   : TestReg<0x01,  "d0">,  DwarfRegNum<[0]>;*
>
> and then in InstInfo.td
> *bits<6> Dr;
> let Inst{5-3} = Dr{2-0};*
>
> assuming D0 is passed to $Dr, what I get in the encoding is 110, which I
> think is the bit 0 to 2 of what is the returned value in the
> TestGenAsmMatcher.inc.
> I mean, at the end, Inst{5-3} is getting a value which is not 001.
> What am I doing wrong?
>

I'm assuming that your TestReg definition assigns the 0x01 to the 
HWEncoding field.

In an instruction definition, the way that tablegen assigns values from 
the parameters is that it goes over all undefined fields in the 
instruction class and assigns the values of the first argument to the 
first undefined field, the value of the second argument to the second 
undefined field, etc.  What may be happening is that the D0 that you 
pass to the pattern is assigned to a different field that you expect.

You can get all the expanded records from tablegen:

llvm-tblgen -print-records -I [llvm source]/lib/Target/[your target] -I 
[llvm source]/lib/Target -I [llvm source]/include [llvm 
source]/lib/Target/Hexagon/[your target].td

You should see the full class corresponding to the instruction 
definition, and see what fields in it are undefined.  One thing that I'm 
not sure about is how table-gen handles types, for example, what it does 
if the argument is bits<5>, but there is an undefined field of type 
bits<1>.  I don't know if it will skip it or truncate it to 1 bit.

-Krzysztof

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