<div dir="ltr"><div><div>Hi Krzysztof,<br></div><br></div>Thanks for your reply. I wanted to assign the hardware encoding to the Instruction bits like the link below:<br><div><div><div><div><br><a href="https://groups.google.com/d/msg/llvm-dev/BfUmfIWYRM8/6JGXQf1gCQAJ">https://groups.google.com/d/msg/llvm-dev/BfUmfIWYRM8/6JGXQf1gCQAJ</a><br><br></div><div>but, at the end, what is assigned to the Inst is, I suppose, the register ID not the encoding!<br><br></div><div>to be more clear, I do the followings:<br><b>def D0 : TestReg<0x01, "d0">, DwarfRegNum<[0]>;</b><br><br></div><div>and then in InstInfo.td<br><b>bits<6> Dr;<br>let Inst{5-3} = Dr{2-0};</b><br><br></div><div>assuming D0 is passed to $Dr, what I get in the encoding is 110, which I think is the bit 0 to 2 of what is the returned value in the TestGenAsmMatcher.inc.<br></div><div>I mean, at the end, Inst{5-3} is getting a value which is not 001.<br></div><div>What am I doing wrong?<br><br></div><div><br></div><div><br></div><div><br><br></div></div></div></div></div><div class="gmail_extra"><br><div class="gmail_quote">On Thu, Sep 17, 2015 at 3:05 PM, Krzysztof Parzyszek via llvm-dev <span dir="ltr"><<a href="mailto:llvm-dev@lists.llvm.org" target="_blank">llvm-dev@lists.llvm.org</a>></span> wrote:<br><blockquote class="gmail_quote" style="margin:0 0 0 .8ex;border-left:1px #ccc solid;padding-left:1ex"><span class="">On 9/17/2015 7:04 AM, Sky Flyer via llvm-dev wrote:<br>
<blockquote class="gmail_quote" style="margin:0 0 0 .8ex;border-left:1px #ccc solid;padding-left:1ex">
It seems like d0 is always 14!<br>
I check it with ARMGenAsmMatcher.inc it was the same!<br>
How is it possible? because it should give the same register value that<br>
matches the underlying platform not any autogenerated value!?<br>
</blockquote>
<br></span>
The returned number is the register id as defined in <YourTarget>GenRegisterInfo.inc. These numbers don't have any meaning other than to represent a particular register. The 0x01 would be the encoding used in generating the binary.<br>
<br>
The D0 has id 14 on ARM because there are 13 other registers preceding it:<br>
namespace ARM {<br>
enum {<br>
NoRegister,<br>
APSR = 1,<br>
APSR_NZCV = 2,<br>
CPSR = 3,<br>
FPEXC = 4,<br>
FPINST = 5,<br>
FPSCR = 6,<br>
FPSCR_NZCV = 7,<br>
FPSID = 8,<br>
ITSTATE = 9,<br>
LR = 10,<br>
PC = 11,<br>
SP = 12,<br>
SPSR = 13,<br>
D0 = 14,<br>
...<span class="HOEnZb"><font color="#888888"><br>
<br>
-Krzysztof<br>
<br>
-- <br>
Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, hosted by The Linux Foundation<br>
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