[llvm] [RISCV][P-ext] Add packed sign and zero extend intrinsics (PR #208685)

[Craig Topper via llvm-commits]

================
@@ -17771,6 +17839,29 @@ static SDValue combineNarrowableShiftedLoad(SDNode *N, SelectionDAG &DAG) {
                      DAG.getShiftAmountConstant(ShiftAmt, VT, DL));
 }
 
+static SDValue combinePZExt(SDNode *N, SelectionDAG &DAG,
----------------
topperc wrote:

I think maybe we should enable `DAGCombiner::XformToShuffleWithZero` by implementing `TLI.isVectorClearMaskLegal` and then teach shuffle lowering how to form `RISCVISD::PPAIRE`?

https://github.com/llvm/llvm-project/pull/208685