[llvm] [RISCV][P-ext] Add packed sign and zero extend intrinsics (PR #208685)

[Craig Topper via llvm-commits]

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@@ -2095,6 +2095,16 @@ class RVPBinaryIntrinsic
                             [IntrNoMem, IntrSpeculatable]>;
   def int_riscv_pmerge : RVPTernaryIntrinsic;
 
+  // Packed Sign and Zero Extend.
+  class RVPExtIntrinsic
+      : DefaultAttrsIntrinsic<[llvm_anyvector_ty],
+                              [LLVMMatchType<0>],
+                              [IntrNoMem, IntrSpeculatable]>;
+  def int_riscv_psext_b : RVPExtIntrinsic;
+  def int_riscv_psext_h : RVPExtIntrinsic;
+  def int_riscv_pzext_b : RVPExtIntrinsic;
+  def int_riscv_pzext_h : RVPExtIntrinsic;
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topperc wrote:

These intrinsics don't change the element size. The zero/sign extend the element in place.

https://github.com/llvm/llvm-project/pull/208685