[llvm] [RISCV][P-ext] Add packed sign and zero extend intrinsics (PR #208685)

[via llvm-commits]

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@@ -11961,6 +11961,21 @@ static unsigned getRVPShiftOpcode(Intrinsic::ID IntNo) {
   }
 }
 
+static SDValue lowerPZExt(SDValue Src, const SDLoc &DL, SelectionDAG &DAG,
+                          const RISCVSubtarget &Subtarget) {
+  MVT VT = Src.getSimpleValueType();
+  MVT PPairVT =
+      MVT::getVectorVT(MVT::getIntegerVT(VT.getScalarSizeInBits() / 2),
+                       VT.getVectorNumElements() * 2);
+  Src = DAG.getBitcast(PPairVT, Src);
+  unsigned ZeroReg = !Subtarget.is64Bit() && PPairVT.getSizeInBits() == 64
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sihuan wrote:

Switched to a zero `SPLAT_VECTOR` in `lowerPZExt`

https://github.com/llvm/llvm-project/pull/208685