[llvm] [AArch64][SVE] Support lowering masked loads/stores of <4 x bf16> and <8 x bf16> (PR #208744)

[Shanzhi Chen via llvm-commits]

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chenshanzhi wrote:

@sdesmalen-arm  Thanks for bringing this up. I filed a issue to track the the unexpected code generation for fixed-length vectors of bf16 when using `-mattr="+sve"` without `"+bf16"`:
https://github.com/llvm/llvm-project/issues/209758



https://github.com/llvm/llvm-project/pull/208744