[llvm] [AArch64][SVE] Support lowering masked loads/stores of <4 x bf16> and <8 x bf16> (PR #208744)

[Shanzhi Chen via llvm-commits]

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chenshanzhi wrote:

Yes. I found several failed tests are improvements in code generation.

```
Failed Tests (5):
  LLVM :: CodeGen/AArch64/sve-fixed-length-extract-subvector.ll
  LLVM :: CodeGen/AArch64/sve-fixed-length-fp-compares.ll
  LLVM :: CodeGen/AArch64/sve-fixed-length-splat-segment.ll
  LLVM :: CodeGen/AArch64/sve-indexed-arithmetic.ll
  LLVM :: CodeGen/AArch64/sve2p1-vector-shuffles.ll
```

In this 5 failed tests listed before, I think the other 4 tests (except `sve-fixed-length-fp-compares.ll) are all improvements.

https://github.com/llvm/llvm-project/pull/208744