[llvm] [AArch64][llvm][tablegen] Restrict luti6 assembly (4 regs, 8-bit) to 0 <= Zn <= 7 (PR #200751)

Jonathan Thackray via llvm-commits llvm-commits at lists.llvm.org
Mon Jul 13 04:09:19 PDT 2026

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https://github.com/jthackray closed https://github.com/llvm/llvm-project/pull/200751

Previous message: [llvm] [AArch64][llvm][tablegen] Restrict luti6 assembly (4 regs, 8-bit) to 0 <= Zn <= 7 (PR #200751)
Next message: [llvm] [SDAG][X86] Form pseudo fmin/fmax from select_cc (PR #208717)
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