[llvm] [AArch64][llvm][tablegen] Restrict luti6 assembly (4 regs, 8-bit) to 0 <= Zn <= 7 (PR #200751)

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Lukacma wrote:

I think we can also get rid of this class and DecodeZPR4Mul4RegisterClass. But that's probably better to do in a separate patch.

https://github.com/llvm/llvm-project/pull/200751