[llvm] [SDAG][X86] Form pseudo fmin/fmax from select_cc (PR #208717)
Simon Pilgrim via llvm-commits
llvm-commits at lists.llvm.org
Mon Jul 13 04:00:31 PDT 2026
================
@@ -13194,23 +13188,46 @@ static SDValue combineSelectToPseudoMinMax(SelectionDAG &DAG, SDNode *N) {
}
if (!Opcode)
- return SDValue();
+ return Invalid;
if (IsStrict)
Opcode = Opcode == ISD::PSEUDO_FMIN ? ISD::STRICT_PSEUDO_FMIN
: ISD::STRICT_PSEUDO_FMAX;
if (!TLI.isOperationLegalOrCustom(Opcode, VT))
+ return Invalid;
+
+ return {Opcode, LHS, RHS};
+}
+
+static SDValue combineSelectToPseudoMinMax(SelectionDAG &DAG, SDNode *N) {
+ SDLoc DL(N);
+ SDValue Cond = N->getOperand(0);
+ SDValue LHS = N->getOperand(1);
+ SDValue RHS = N->getOperand(2);
+ EVT VT = LHS.getValueType();
+ if ((Cond.getOpcode() != ISD::SETCC &&
+ Cond.getOpcode() != ISD::STRICT_FSETCCS))
+ return SDValue();
+
+ bool IsStrict = Cond->isStrictFPOpcode();
+ ISD::CondCode CC =
+ cast<CondCodeSDNode>(Cond.getOperand(IsStrict ? 3 : 2))->get();
+ SDValue Op0 = Cond.getOperand(IsStrict ? 1 : 0);
+ SDValue Op1 = Cond.getOperand(IsStrict ? 2 : 1);
+ auto [Opcode, NewLHS, NewRHS] = combineSelectCCToPseudoMinMax(
+ DAG, DL, CC, Op0, Op1, LHS, RHS, N->getFlags(), IsStrict);
+ if (!Opcode)
return SDValue();
// Propagate fast-math-flags.
SelectionDAG::FlagInserter FlagsInserter(DAG, N->getFlags());
if (IsStrict) {
- SDValue Ret = DAG.getNode(Opcode, DL, {N->getValueType(0), MVT::Other},
- {Cond.getOperand(0), LHS, RHS});
+ SDValue Ret = DAG.getNode(Opcode, DL, {VT, MVT::Other},
+ {Cond.getOperand(0), NewLHS, NewRHS});
DAG.ReplaceAllUsesOfValueWith(Cond.getValue(1), Ret.getValue(1));
return Ret;
}
- return DAG.getNode(Opcode, DL, N->getValueType(0), LHS, RHS);
+ return DAG.getNode(Opcode, DL, VT, NewLHS, NewRHS);
----------------
RKSimon wrote:
I get splitting the SDNode into component operands - but why do we need to return the opcode/ops and then create the nodes in the caller?
https://github.com/llvm/llvm-project/pull/208717
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