[llvm] [AArch64] Allocate two emergency spill slots for MTE to fix register … (PR #186505)

[Florian Mayer via llvm-commits]

================
@@ -2726,18 +2730,44 @@ void AArch64FrameLowering::determineCalleeSaves(MachineFunction &MF,
       }
     }
 
-    // If we didn't find an extra callee-saved register to spill, create
-    // an emergency spill slot.
-    if (!ExtraCSSpill || MF.getRegInfo().isPhysRegUsed(ExtraCSSpill)) {
-      const TargetRegisterInfo *TRI = MF.getSubtarget().getRegisterInfo();
+    auto CreateEmergencySpillSlot = [&RS, &MFI](const TargetRegisterInfo *TRI) {
       const TargetRegisterClass &RC = AArch64::GPR64RegClass;
       unsigned Size = TRI->getSpillSize(RC);
       Align Alignment = TRI->getSpillAlign(RC);
       int FI = MFI.CreateSpillStackObject(Size, Alignment);
       RS->addScavengingFrameIndex(FI);
+      return FI;
+    };
+    // If we didn't find an extra callee-saved register to spill, create
+    // an emergency spill slot.
+    if (!ExtraCSSpill || MF.getRegInfo().isPhysRegUsed(ExtraCSSpill)) {
+      auto FI = CreateEmergencySpillSlot(MF.getSubtarget().getRegisterInfo());
       LLVM_DEBUG(dbgs() << "No available CS registers, allocated fi#" << FI
                         << " as the emergency spill slot.\n");
     }
+
+    // FIX: MTE emitLoop() can spawn two post-RA virtual registers
+    // simultaneously (BaseReg and SizeReg). We must ensure the scavenger has a
+    // SECOND scratch space available, regardless of whether the first came from
+    // ExtraCSSpill or the baseline emergency spill slot above.
+    if (StackTaggingMergeSetTag) {
+      bool FoundSTG = false;
+      for (auto &MBB : MF) {
+        for (auto &MI : MBB) {
----------------
fmayer wrote:

```cc
bool HasMergableSTG(const MachineFunction& MF) {
  for (auto &MBB : MF)
    if (any_of(MBB, [](const auto& MI) { return isMergeableSTG(MI); })
      return true;
  return false;
}
```

https://github.com/llvm/llvm-project/pull/186505