[llvm] [AArch64] Optimize vector slide shuffles with zeros to use shift instructions (PR #185170)

[David Green via llvm-commits]

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@@ -15357,6 +15438,24 @@ SDValue AArch64TargetLowering::LowerVECTOR_SHUFFLE(SDValue Op,
                                   DL);
   }
 
+  if (VT.getSizeInBits() == 64) {
+    unsigned ShiftAmount;
+    bool IsRightShift;
+    if (isSlideWithZerosMask(ShuffleMask, VT, V1, V2, ShiftAmount,
+                             IsRightShift)) {
+      SDValue DataVec = ISD::isBuildVectorAllZeros(V1.getNode()) ? V2 : V1;
+
+      // Bitcast to v1i64 for scalar shift
+      SDValue Vec64 = DAG.getBitcast(MVT::v1i64, DataVec);
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davemgreen wrote:

Create a NVCAST, as it works more like how you would expect even on big endian.

https://github.com/llvm/llvm-project/pull/185170