[llvm] [AArch64] Optimize vector slide shuffles with zeros to use shift instructions (PR #185170)

[David Green via llvm-commits]

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@@ -15357,6 +15438,24 @@ SDValue AArch64TargetLowering::LowerVECTOR_SHUFFLE(SDValue Op,
                                   DL);
   }
 
+  if (VT.getSizeInBits() == 64) {
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davemgreen wrote:

Is it possible / profitable to handle other vector sizes? Like a v4i32 could be handled if the mask was <z, 0, 1, 2, z, 4, 5, 6, ...>, where z = form the zero vector.

https://github.com/llvm/llvm-project/pull/185170