[llvm] [AArch64] Optimize vector slide shuffles with zeros to use shift instructions (PR #185170)

[David Green via llvm-commits]

================
@@ -14578,6 +14587,78 @@ static bool isEXTMask(ArrayRef<int> M, EVT VT, bool &ReverseEXT,
   return true;
 }
 
+
+/// Flag slide shuffle patterns where one operand is zeros.
+/// Left slide: shufflevector %v, zeros, <1,2,3,...> -> ushr
+/// Right slide: shufflevector zeros, %v, <N-1,N,N+1,...> -> shl
+static bool isSlideWithZerosMask(ArrayRef<int> M, EVT VT, SDValue V1,
+                                 SDValue V2, unsigned &ShiftAmount,
+                                 bool &IsRightShift) {
+  // Only handle 64-bit vectors
+  if (VT.getSizeInBits() != 64)
+    return false;
+
+  unsigned NumElts = VT.getVectorNumElements();
----------------
davemgreen wrote:

Can this use ShuffleVectorSDNode::commuteMask(CommutedMask) to canonicalize the zero the the RHS, we so only need to handle one case?

https://github.com/llvm/llvm-project/pull/185170