[llvm] [AArch64][llvm] Gate some `tlbip` insns with either +tlbid or +d128 (PR #178913)

[Jonathan Thackray via llvm-commits]

================
@@ -453,6 +453,31 @@ struct SysAliasOptionalReg : SysAlias {
       : SysAlias(N, E, F), NeedsReg(R), OptionalReg(O) {}
 };
 
+struct TLBIPSysAlias : SysAliasOptionalReg {
+  bool d128orTLBID;
+  inline static const FeatureBitset D128OrTLBIDMask =
+      FeatureBitset({llvm::AArch64::FeatureD128, llvm::AArch64::FeatureTLBID});
+
+  constexpr TLBIPSysAlias(const char *N, uint16_t E, bool R, bool O,
+                          FeatureBitset F, bool D128OrTLBID)
+      : SysAliasOptionalReg(N, E, R, O, F), d128orTLBID(D128OrTLBID) {}
+
+  bool allowTLBID() const { return d128orTLBID; }
+
+  bool haveFeatures(FeatureBitset ActiveFeatures) const {
+    if (ActiveFeatures[llvm::AArch64::FeatureAll])
+      return true;
+
+    FeatureBitset Required = FeaturesRequired;
+    if (d128orTLBID)
+      Required &= ~D128OrTLBIDMask;
+
+    return (Required & ActiveFeatures) == Required &&
+           (!d128orTLBID || ActiveFeatures[llvm::AArch64::FeatureD128] ||
+            ActiveFeatures[llvm::AArch64::FeatureTLBID]);
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jthackray wrote:

Ok, thanks, done.

https://github.com/llvm/llvm-project/pull/178913