[llvm] [AArch64][llvm] Gate some `tlbip` insns with either +tlbid or +d128 (PR #178913)

[Jonathan Thackray via llvm-commits]

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@@ -857,7 +857,7 @@ def : TIndex<"nb", 0b1>;
 //===----------------------------------------------------------------------===//
 
 class TLBICommon<string name, bits<3> op1, bits<4> crn, bits<4> crm,
-                 bits<3> op2, bit needsreg, bit optionalreg> {
+                 bits<3> op2, bit needsreg, bit optionalreg, bit allowTLBID> {
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jthackray wrote:

Sure, done.

https://github.com/llvm/llvm-project/pull/178913