[llvm] [AMDGPU] Disable negative imm offset for async load/store instructions (PR #185078)

[Stanislav Mekhanoshin via llvm-commits]

rampitec wrote:

> > Remember offset only uses 16 bits on the LDS side.
> 
> I think that kind of instruction should not be generated in the first place, aka. the use of intrinsics should be checked, since the same offset is used for both, but I still added some defensive code for that.

It is the single imm in the intrinsic for both, but this pass can make it illegal w/o your patch. I'd probably shrink the intrinsic imm to i16 though.

https://github.com/llvm/llvm-project/pull/185078