[llvm] [AMDGPU] Disable negative imm offset for async load/store instructions (PR #185078)

[Shilei Tian via llvm-commits]

shiltian wrote:

> Remember offset only uses 16 bits on the LDS side.

I think that kind of instruction should not be generated in the first place, aka. the use of intrinsics should be checked, since the same offset is used for both, but I still generate some defensive code for that.

https://github.com/llvm/llvm-project/pull/185078