[llvm] [AMDGPU] Disable negative imm offset for async load/store instructions (PR #185078)

[Shilei Tian via llvm-commits]

shiltian wrote:

> It is the single imm in the intrinsic for both, but this pass can make it illegal w/o your patch. I'd probably shrink the intrinsic imm to i16 though.

Yeah, I'll make the change in a follow-up.

Other than that, does this PR look good after the anchor choice change?

https://github.com/llvm/llvm-project/pull/185078