[llvm] [RISCV] Add register overlap checks to the assembler for vector indexed segment load (PR #184569)

[Craig Topper via llvm-commits]

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@@ -1900,6 +1903,7 @@ let Predicates = [HasVInstructionsI64, IsRV64] in {
         : VIndexedSegmentLoad<nfields, MOPLDIndexedOrder, LSWidth64,
                               "vloxseg" #nfields #"ei64.v">,
           VLXSEGSchedMC<nfields, 64, isOrdered=1>;
+    } //VS1VS2Constraint = VS2Constraint
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topperc wrote:

```suggestion
    } // VS1VS2Constraint = VS2Constraint
```

https://github.com/llvm/llvm-project/pull/184569