[llvm] [RISCV] Add register overlap checks to the assembler for vector indexed segment load (PR #184569)

[via llvm-commits]

https://github.com/joshua-arch1 updated https://github.com/llvm/llvm-project/pull/184569

>From 10aa94097630147dde4bacd44bb9b24c1a7916be Mon Sep 17 00:00:00 2001
From: joshua-arch1 <cooper.joshua at linux.alibaba.com>
Date: Thu, 5 Mar 2026 16:28:04 +0800
Subject: [PATCH] [RISCV] Add register overlap checks to the assembler for
 vector indexed segment load

---
 llvm/lib/Target/RISCV/RISCVInstrInfoV.td |  4 ++
 llvm/test/MC/RISCV/rvv/zvlsseg-invalid.s | 66 ++++++++++++++++++++++++
 2 files changed, 70 insertions(+)
 create mode 100644 llvm/test/MC/RISCV/rvv/zvlsseg-invalid.s

diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoV.td b/llvm/lib/Target/RISCV/RISCVInstrInfoV.td
index bb8d26662ae4e..8f97fe5f71049 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfoV.td
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfoV.td
@@ -1843,6 +1843,7 @@ let Predicates = [HasVInstructions] in {
         VSSSEGSchedMC<nfields, eew>;
 
       // Vector Indexed Instructions
+      let VS1VS2Constraint = VS2Constraint in {
       def VLUXSEG#nfields#EI#eew#_V :
         VIndexedSegmentLoad<nfields, MOPLDIndexedUnord, w,
                             "vluxseg"#nfields#"ei"#eew#".v">,
@@ -1853,6 +1854,7 @@ let Predicates = [HasVInstructions] in {
                             "vloxseg"#nfields#"ei"#eew#".v">,
         RISCVVXMemOpMC<eew, Ordered=true, Store=false, N=nfields>,
         VLXSEGSchedMC<nfields, eew, isOrdered=1>;
+      } //VS1VS2Constraint = VS2Constraint
       def VSUXSEG#nfields#EI#eew#_V :
         VIndexedSegmentStore<nfields, MOPSTIndexedUnord, w,
                              "vsuxseg"#nfields#"ei"#eew#".v">,
@@ -1892,6 +1894,7 @@ let Predicates = [HasVInstructionsI64] in {
 let Predicates = [HasVInstructionsI64, IsRV64] in {
   foreach nfields = 2 - 8 in {
     // Vector Indexed Segment Instructions
+    let VS1VS2Constraint = VS2Constraint in {
     def VLUXSEG #nfields #EI64_V
         : VIndexedSegmentLoad<nfields, MOPLDIndexedUnord, LSWidth64,
                               "vluxseg" #nfields #"ei64.v">,
@@ -1900,6 +1903,7 @@ let Predicates = [HasVInstructionsI64, IsRV64] in {
         : VIndexedSegmentLoad<nfields, MOPLDIndexedOrder, LSWidth64,
                               "vloxseg" #nfields #"ei64.v">,
           VLXSEGSchedMC<nfields, 64, isOrdered=1>;
+    } //VS1VS2Constraint = VS2Constraint
     def VSUXSEG #nfields #EI64_V
         : VIndexedSegmentStore<nfields, MOPSTIndexedUnord, LSWidth64,
                                "vsuxseg" #nfields #"ei64.v">,
diff --git a/llvm/test/MC/RISCV/rvv/zvlsseg-invalid.s b/llvm/test/MC/RISCV/rvv/zvlsseg-invalid.s
new file mode 100644
index 0000000000000..900f85849e4f1
--- /dev/null
+++ b/llvm/test/MC/RISCV/rvv/zvlsseg-invalid.s
@@ -0,0 +1,66 @@
+# RUN: not llvm-mc -triple=riscv64 --mattr=+v %s 2>&1 \
+# RUN:        | FileCheck %s --check-prefix=CHECK-ERROR
+ 
+vluxseg2ei8.v v8, (a0), v8, v0.t
+# CHECK-ERROR: the destination vector register group cannot overlap the source vector register group
+# CHECK-ERROR-LABEL: vluxseg2ei8.v v8, (a0), v8, v0.t
+ 
+vluxseg2ei8.v v8, (a0), v8
+# CHECK-ERROR: the destination vector register group cannot overlap the source vector register group
+# CHECK-ERROR-LABEL: vluxseg2ei8.v v8, (a0), v8
+ 
+vluxseg2ei16.v v8, (a0), v8, v0.t
+# CHECK-ERROR: the destination vector register group cannot overlap the source vector register group
+# CHECK-ERROR-LABEL: vluxseg2ei16.v v8, (a0), v8, v0.t
+ 
+vluxseg2ei16.v v8, (a0), v8
+# CHECK-ERROR: the destination vector register group cannot overlap the source vector register group
+# CHECK-ERROR-LABEL: vluxseg2ei16.v v8, (a0), v8
+ 
+vluxseg2ei32.v v8, (a0), v8, v0.t
+# CHECK-ERROR: the destination vector register group cannot overlap the source vector register group
+# CHECK-ERROR-LABEL: vluxseg2ei32.v v8, (a0), v8, v0.t
+ 
+vluxseg2ei32.v v8, (a0), v8
+# CHECK-ERROR: the destination vector register group cannot overlap the source vector register group
+# CHECK-ERROR-LABEL: vluxseg2ei32.v v8, (a0), v8
+ 
+vluxseg2ei64.v v8, (a0), v8, v0.t
+# CHECK-ERROR: the destination vector register group cannot overlap the source vector register group
+# CHECK-ERROR-LABEL: vluxseg2ei64.v v8, (a0), v8, v0.t
+ 
+vluxseg2ei64.v v8, (a0), v8
+# CHECK-ERROR: the destination vector register group cannot overlap the source vector register group
+# CHECK-ERROR-LABEL: vluxseg2ei64.v v8, (a0), v8
+ 
+vloxseg2ei8.v v8, (a0), v8, v0.t
+# CHECK-ERROR: the destination vector register group cannot overlap the source vector register group
+# CHECK-ERROR-LABEL: vloxseg2ei8.v v8, (a0), v8, v0.t
+ 
+vloxseg2ei8.v v8, (a0), v8
+# CHECK-ERROR: the destination vector register group cannot overlap the source vector register group
+# CHECK-ERROR-LABEL: vloxseg2ei8.v v8, (a0), v8
+ 
+vloxseg2ei16.v v8, (a0), v8, v0.t
+# CHECK-ERROR: the destination vector register group cannot overlap the source vector register group
+# CHECK-ERROR-LABEL: vloxseg2ei16.v v8, (a0), v8, v0.t
+ 
+vloxseg2ei16.v v8, (a0), v8
+# CHECK-ERROR: the destination vector register group cannot overlap the source vector register group
+# CHECK-ERROR-LABEL: vloxseg2ei16.v v8, (a0), v8
+ 
+vloxseg2ei32.v v8, (a0), v8, v0.t
+# CHECK-ERROR: the destination vector register group cannot overlap the source vector register group
+# CHECK-ERROR-LABEL: vloxseg2ei32.v v8, (a0), v8, v0.t
+ 
+vloxseg2ei32.v v8, (a0), v8
+# CHECK-ERROR: the destination vector register group cannot overlap the source vector register group
+# CHECK-ERROR-LABEL: vloxseg2ei32.v v8, (a0), v8
+ 
+vloxseg2ei64.v v8, (a0), v8, v0.t
+# CHECK-ERROR: the destination vector register group cannot overlap the source vector register group
+# CHECK-ERROR-LABEL: vloxseg2ei64.v v8, (a0), v8, v0.t
+ 
+vloxseg2ei64.v v8, (a0), v8
+# CHECK-ERROR: the destination vector register group cannot overlap the source vector register group
+# CHECK-ERROR-LABEL: vloxseg2ei64.v v8, (a0), v8