[llvm] [RISCV] Add register overlap checks to the assembler for vector indexed segment load (PR #184569)

[Craig Topper via llvm-commits]

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@@ -1853,6 +1854,7 @@ let Predicates = [HasVInstructions] in {
                             "vloxseg"#nfields#"ei"#eew#".v">,
         RISCVVXMemOpMC<eew, Ordered=true, Store=false, N=nfields>,
         VLXSEGSchedMC<nfields, eew, isOrdered=1>;
+      } //VS1VS2Constraint = VS2Constraint
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topperc wrote:

```suggestion
      } // VS1VS2Constraint = VS2Constraint
```

https://github.com/llvm/llvm-project/pull/184569