[llvm] [AArch64] Add scal_to_vec patterns for SIMD convert intrinsics (PR #172837)

[Kerry McLaughlin via llvm-commits]

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@@ -607,3 +607,335 @@ define  float @fcvtzu_1s1s_simd(float %a) {
   %d = bitcast i32 %vcvtah_s32_f32 to float
   ret float %d
 }
+
+;
+; Intriniscs (scalar_to_vector)
+;
+
+define <1 x i64> @fcvtas_1d1s_scalar_to_vector_simd(float %A) nounwind {
+; CHECK-LABEL: fcvtas_1d1s_scalar_to_vector_simd:
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    fcvtas d0, s0
+; CHECK-NEXT:    ret
+  %i = call i64 @llvm.aarch64.neon.fcvtas.i64.f32(float %A)
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kmclaughlin-arm wrote:

Is it worth updating the tests with `%i` to something like `%vcvtah_s64_f32` to match the others?

https://github.com/llvm/llvm-project/pull/172837