[llvm] [RISCV] Handle more cases when combining (vfmv.s.f (extract_subvector X, 0)) (PR #154175)
Min-Yih Hsu via llvm-commits
llvm-commits at lists.llvm.org
Tue Aug 19 09:42:40 PDT 2025
https://github.com/mshockwave updated https://github.com/llvm/llvm-project/pull/154175
>From 74512706c71be5bda852b8285e0e941d4175e5bb Mon Sep 17 00:00:00 2001
From: Min-Yih Hsu <min.hsu at sifive.com>
Date: Mon, 18 Aug 2025 10:35:27 -0700
Subject: [PATCH 1/3] Pre-commit test
---
.../CodeGen/RISCV/rvv/redundant-vfmvsf.ll | 28 +++++++++++++++++++
1 file changed, 28 insertions(+)
create mode 100644 llvm/test/CodeGen/RISCV/rvv/redundant-vfmvsf.ll
diff --git a/llvm/test/CodeGen/RISCV/rvv/redundant-vfmvsf.ll b/llvm/test/CodeGen/RISCV/rvv/redundant-vfmvsf.ll
new file mode 100644
index 0000000000000..6041d736f3411
--- /dev/null
+++ b/llvm/test/CodeGen/RISCV/rvv/redundant-vfmvsf.ll
@@ -0,0 +1,28 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
+; RUN: llc -mtriple=riscv64 -mattr='+v,+zvl512b' < %s | FileCheck %s
+
+define <2 x float> @redundant_vfmv(<2 x float> %arg0, <64 x float> %arg1, <64 x float> %arg2) {
+; CHECK-LABEL: redundant_vfmv:
+; CHECK: # %bb.0:
+; CHECK-NEXT: li a0, 64
+; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, ma
+; CHECK-NEXT: vfredusum.vs v9, v12, v8
+; CHECK-NEXT: vsetivli zero, 1, e32, mf2, ta, ma
+; CHECK-NEXT: vslidedown.vi v8, v8, 1
+; CHECK-NEXT: vfmv.f.s fa5, v8
+; CHECK-NEXT: vfmv.s.f v8, fa5
+; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, ma
+; CHECK-NEXT: vfredusum.vs v8, v16, v8
+; CHECK-NEXT: vfmv.f.s fa5, v8
+; CHECK-NEXT: vsetivli zero, 2, e32, mf2, ta, ma
+; CHECK-NEXT: vrgather.vi v8, v9, 0
+; CHECK-NEXT: vfslide1down.vf v8, v8, fa5
+; CHECK-NEXT: ret
+ %s0 = extractelement <2 x float> %arg0, i64 0
+ %r0 = tail call reassoc float @llvm.vector.reduce.fadd.v64f32(float %s0, <64 x float> %arg1)
+ %a0 = insertelement <2 x float> poison, float %r0, i64 0
+ %s1 = extractelement <2 x float> %arg0, i64 1
+ %r1 = tail call reassoc float @llvm.vector.reduce.fadd.v64f32(float %s1, <64 x float> %arg2)
+ %a1 = insertelement <2 x float> %a0, float %r1, i64 1
+ ret <2 x float> %a1
+}
>From 3373776f591ec10662f89fd7e5c201fda25aaa19 Mon Sep 17 00:00:00 2001
From: Min-Yih Hsu <min.hsu at sifive.com>
Date: Mon, 18 Aug 2025 10:23:11 -0700
Subject: [PATCH 2/3] [RISCV] Handle more cases when combining (vfmv_s_f
(extract_subvector X, 0))
Co-Authored-By: Craig Topper <craig.topper at sifive.com>
---
llvm/lib/Target/RISCV/RISCVISelLowering.cpp | 16 +++++++++++++---
llvm/test/CodeGen/RISCV/rvv/redundant-vfmvsf.ll | 2 --
2 files changed, 13 insertions(+), 5 deletions(-)
diff --git a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
index ce03818b49502..72069c547c50e 100644
--- a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
+++ b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
@@ -20738,12 +20738,22 @@ SDValue RISCVTargetLowering::PerformDAGCombine(SDNode *N,
isNullConstant(Src.getOperand(1)) &&
Src.getOperand(0).getValueType().isScalableVector()) {
EVT VT = N->getValueType(0);
- EVT SrcVT = Src.getOperand(0).getValueType();
+ SDValue EVSrc = Src.getOperand(0);
+ EVT SrcVT = EVSrc.getValueType();
assert(SrcVT.getVectorElementType() == VT.getVectorElementType());
// Widths match, just return the original vector.
if (SrcVT == VT)
- return Src.getOperand(0);
- // TODO: Use insert_subvector/extract_subvector to change widen/narrow?
+ return EVSrc;
+ SDLoc DL(N);
+ // Width is narrower, using insert_subvector.
+ if (SrcVT.getVectorMinNumElements() < VT.getVectorMinNumElements()) {
+ return DAG.getNode(ISD::INSERT_SUBVECTOR, DL, VT, DAG.getUNDEF(VT),
+ EVSrc,
+ DAG.getConstant(0, DL, Subtarget.getXLenVT()));
+ }
+ // Width is wider, using extract_subvector.
+ return DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, VT, EVSrc,
+ DAG.getConstant(0, DL, Subtarget.getXLenVT()));
}
[[fallthrough]];
}
diff --git a/llvm/test/CodeGen/RISCV/rvv/redundant-vfmvsf.ll b/llvm/test/CodeGen/RISCV/rvv/redundant-vfmvsf.ll
index 6041d736f3411..da912bf401ec0 100644
--- a/llvm/test/CodeGen/RISCV/rvv/redundant-vfmvsf.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/redundant-vfmvsf.ll
@@ -9,8 +9,6 @@ define <2 x float> @redundant_vfmv(<2 x float> %arg0, <64 x float> %arg1, <64 x
; CHECK-NEXT: vfredusum.vs v9, v12, v8
; CHECK-NEXT: vsetivli zero, 1, e32, mf2, ta, ma
; CHECK-NEXT: vslidedown.vi v8, v8, 1
-; CHECK-NEXT: vfmv.f.s fa5, v8
-; CHECK-NEXT: vfmv.s.f v8, fa5
; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, ma
; CHECK-NEXT: vfredusum.vs v8, v16, v8
; CHECK-NEXT: vfmv.f.s fa5, v8
>From abc1e1192481cf4f0a45bbbff6fa10bf31d33a25 Mon Sep 17 00:00:00 2001
From: Min-Yih Hsu <min.hsu at sifive.com>
Date: Tue, 19 Aug 2025 09:42:21 -0700
Subject: [PATCH 3/3] fixup! Address review comments
---
llvm/lib/Target/RISCV/RISCVISelLowering.cpp | 8 ++++----
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
index 72069c547c50e..933dd36c3c472 100644
--- a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
+++ b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
@@ -20739,14 +20739,14 @@ SDValue RISCVTargetLowering::PerformDAGCombine(SDNode *N,
Src.getOperand(0).getValueType().isScalableVector()) {
EVT VT = N->getValueType(0);
SDValue EVSrc = Src.getOperand(0);
- EVT SrcVT = EVSrc.getValueType();
- assert(SrcVT.getVectorElementType() == VT.getVectorElementType());
+ EVT EVSrcVT = EVSrc.getValueType();
+ assert(EVSrcVT.getVectorElementType() == VT.getVectorElementType());
// Widths match, just return the original vector.
- if (SrcVT == VT)
+ if (EVSrcVT == VT)
return EVSrc;
SDLoc DL(N);
// Width is narrower, using insert_subvector.
- if (SrcVT.getVectorMinNumElements() < VT.getVectorMinNumElements()) {
+ if (EVSrcVT.getVectorMinNumElements() < VT.getVectorMinNumElements()) {
return DAG.getNode(ISD::INSERT_SUBVECTOR, DL, VT, DAG.getUNDEF(VT),
EVSrc,
DAG.getConstant(0, DL, Subtarget.getXLenVT()));
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