[llvm] [AMDGPU] Add support for store to constant address space (PR #153835)

[Matt Arsenault via llvm-commits]

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@@ -3910,10 +3910,14 @@ SDValue AMDGPUTargetLowering::performLoadCombine(SDNode *N,
 // type.
 SDValue AMDGPUTargetLowering::performStoreCombine(SDNode *N,
                                                   DAGCombinerInfo &DCI) const {
+  StoreSDNode *SN = cast<StoreSDNode>(N);
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arsenm wrote:

Just do the selection, that's simpler. There's no point in trying to optimize these, it needs to just be minimally functional. These would ordinarily be deleted as UB in the middle end 

https://github.com/llvm/llvm-project/pull/153835