[llvm] [AMDGPU] Add support for store to constant address space (PR #153835)

[Shilei Tian via llvm-commits]

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@@ -3910,10 +3910,14 @@ SDValue AMDGPUTargetLowering::performLoadCombine(SDNode *N,
 // type.
 SDValue AMDGPUTargetLowering::performStoreCombine(SDNode *N,
                                                   DAGCombinerInfo &DCI) const {
+  StoreSDNode *SN = cast<StoreSDNode>(N);
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shiltian wrote:

> These would ordinarily be deleted as UB in the middle end

Where would be the best place doing it in the middle end? I think it needs to be target dependent, potentially a hook to TTI.

https://github.com/llvm/llvm-project/pull/153835