[llvm] [AMDGPU][True16][CodeGen] select vgpr16 for asm inline 16bit vreg (PR #140946)

[Jay Foad via llvm-commits]

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@@ -16062,7 +16062,8 @@ SITargetLowering::getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI_,
     case 'v':
       switch (BitWidth) {
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jayfoad wrote:

Or even move the handling for the `BitWidth == 16` case inside `getVGPRClassForBitWidth`?

https://github.com/llvm/llvm-project/pull/140946