[llvm] [AMDGPU][True16][CodeGen] select vgpr16 for asm inline 16bit vreg (PR #140946)

[Matt Arsenault via llvm-commits]

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@@ -16062,7 +16062,8 @@ SITargetLowering::getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI_,
     case 'v':
       switch (BitWidth) {
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arsenm wrote:

This reminds me we need constraints for the aligned and unaligned versions of register classes 

https://github.com/llvm/llvm-project/pull/140946