[llvm] dcd62f3 - [SelectionDAG] Rename MemSDNode::getOriginalAlign to getBaseAlign. NFC (#139930)
via llvm-commits
llvm-commits at lists.llvm.org
Fri May 16 09:37:05 PDT 2025
Author: Craig Topper
Date: 2025-05-16T09:37:02-07:00
New Revision: dcd62f3674907b0d31a303b95ea5aa844ffd8238
URL: https://github.com/llvm/llvm-project/commit/dcd62f3674907b0d31a303b95ea5aa844ffd8238
DIFF: https://github.com/llvm/llvm-project/commit/dcd62f3674907b0d31a303b95ea5aa844ffd8238.diff
LOG: [SelectionDAG] Rename MemSDNode::getOriginalAlign to getBaseAlign. NFC (#139930)
This matches the underlying function in MachineMemOperand and how it is
printed when BaseAlign differs from Align.
Added:
Modified:
llvm/include/llvm/CodeGen/SelectionDAGNodes.h
llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
llvm/lib/CodeGen/SelectionDAG/LegalizeFloatTypes.cpp
llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp
llvm/lib/CodeGen/SelectionDAG/LegalizeTypesGeneric.cpp
llvm/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp
llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp
llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
llvm/lib/Target/ARM/ARMISelLowering.cpp
llvm/lib/Target/RISCV/RISCVISelLowering.cpp
llvm/lib/Target/Sparc/SparcISelLowering.cpp
llvm/lib/Target/SystemZ/SystemZISelLowering.cpp
llvm/lib/Target/X86/X86ISelLowering.cpp
Removed:
################################################################################
diff --git a/llvm/include/llvm/CodeGen/SelectionDAGNodes.h b/llvm/include/llvm/CodeGen/SelectionDAGNodes.h
index cfefceea8f0fe..1a373f4c10e78 100644
--- a/llvm/include/llvm/CodeGen/SelectionDAGNodes.h
+++ b/llvm/include/llvm/CodeGen/SelectionDAGNodes.h
@@ -1386,7 +1386,7 @@ class MemSDNode : public SDNode {
bool writeMem() const { return MMO->isStore(); }
/// Returns alignment and volatility of the memory access
- Align getOriginalAlign() const { return MMO->getBaseAlign(); }
+ Align getBaseAlign() const { return MMO->getBaseAlign(); }
Align getAlign() const { return MMO->getAlign(); }
/// Return the SubclassData value, without HasDebugValue. This contains an
diff --git a/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp b/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
index ddaaafe3346bc..4be3363e56987 100644
--- a/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
@@ -12393,8 +12393,8 @@ SDValue DAGCombiner::visitMSTORE(SDNode *N) {
!MST->isCompressingStore() && !MST->isTruncatingStore())
return DAG.getStore(MST->getChain(), SDLoc(N), MST->getValue(),
MST->getBasePtr(), MST->getPointerInfo(),
- MST->getOriginalAlign(),
- MST->getMemOperand()->getFlags(), MST->getAAInfo());
+ MST->getBaseAlign(), MST->getMemOperand()->getFlags(),
+ MST->getAAInfo());
// Try transforming N to an indexed store.
if (CombineToPreIndexedLoadStore(N) || CombineToPostIndexedLoadStore(N))
@@ -12578,7 +12578,7 @@ SDValue DAGCombiner::visitMLOAD(SDNode *N) {
!MLD->isExpandingLoad() && MLD->getExtensionType() == ISD::NON_EXTLOAD) {
SDValue NewLd = DAG.getLoad(
N->getValueType(0), SDLoc(N), MLD->getChain(), MLD->getBasePtr(),
- MLD->getPointerInfo(), MLD->getOriginalAlign(),
+ MLD->getPointerInfo(), MLD->getBaseAlign(),
MLD->getMemOperand()->getFlags(), MLD->getAAInfo(), MLD->getRanges());
return CombineTo(N, NewLd, NewLd.getValue(1));
}
@@ -13618,7 +13618,7 @@ SDValue DAGCombiner::CombineExtLoad(SDNode *N) {
SDValue SplitLoad =
DAG.getExtLoad(ExtType, SDLoc(LN0), SplitDstVT, LN0->getChain(),
BasePtr, LN0->getPointerInfo().getWithOffset(Offset),
- SplitSrcVT, LN0->getOriginalAlign(),
+ SplitSrcVT, LN0->getBaseAlign(),
LN0->getMemOperand()->getFlags(), LN0->getAAInfo());
BasePtr = DAG.getMemBasePlusOffset(BasePtr, TypeSize::getFixed(Stride), DL);
@@ -15175,15 +15175,15 @@ SDValue DAGCombiner::reduceLoadWidth(SDNode *N) {
} else if (CR.getBitWidth() == BitSize)
NewRanges = OldRanges;
}
- Load = DAG.getLoad(
- VT, DL, LN0->getChain(), NewPtr,
- LN0->getPointerInfo().getWithOffset(PtrOff), LN0->getOriginalAlign(),
- LN0->getMemOperand()->getFlags(), LN0->getAAInfo(), NewRanges);
+ Load = DAG.getLoad(VT, DL, LN0->getChain(), NewPtr,
+ LN0->getPointerInfo().getWithOffset(PtrOff),
+ LN0->getBaseAlign(), LN0->getMemOperand()->getFlags(),
+ LN0->getAAInfo(), NewRanges);
} else
Load = DAG.getExtLoad(ExtType, DL, VT, LN0->getChain(), NewPtr,
LN0->getPointerInfo().getWithOffset(PtrOff), ExtVT,
- LN0->getOriginalAlign(),
- LN0->getMemOperand()->getFlags(), LN0->getAAInfo());
+ LN0->getBaseAlign(), LN0->getMemOperand()->getFlags(),
+ LN0->getAAInfo());
// Replace the old load's chain with the new load's chain.
WorklistRemover DeadNodes(*this);
@@ -20599,16 +20599,15 @@ ShrinkLoadReplaceStoreWithStore(const std::pair<unsigned, unsigned> &MaskInfo,
++OpsNarrowed;
if (UseTruncStore)
return DAG.getTruncStore(St->getChain(), SDLoc(St), IVal, Ptr,
- St->getPointerInfo().getWithOffset(StOffset),
- VT, St->getOriginalAlign());
+ St->getPointerInfo().getWithOffset(StOffset), VT,
+ St->getBaseAlign());
// Truncate down to the new size.
IVal = DAG.getNode(ISD::TRUNCATE, SDLoc(IVal), VT, IVal);
- return DAG
- .getStore(St->getChain(), SDLoc(St), IVal, Ptr,
- St->getPointerInfo().getWithOffset(StOffset),
- St->getOriginalAlign());
+ return DAG.getStore(St->getChain(), SDLoc(St), IVal, Ptr,
+ St->getPointerInfo().getWithOffset(StOffset),
+ St->getBaseAlign());
}
/// Look for sequence of load / op / store where op is one of 'or', 'xor', and
@@ -22129,11 +22128,11 @@ SDValue DAGCombiner::replaceStoreOfFPConstant(StoreSDNode *ST) {
AAMDNodes AAInfo = ST->getAAInfo();
SDValue St0 = DAG.getStore(Chain, DL, Lo, Ptr, ST->getPointerInfo(),
- ST->getOriginalAlign(), MMOFlags, AAInfo);
+ ST->getBaseAlign(), MMOFlags, AAInfo);
Ptr = DAG.getMemBasePlusOffset(Ptr, TypeSize::getFixed(4), DL);
SDValue St1 = DAG.getStore(Chain, DL, Hi, Ptr,
ST->getPointerInfo().getWithOffset(4),
- ST->getOriginalAlign(), MMOFlags, AAInfo);
+ ST->getBaseAlign(), MMOFlags, AAInfo);
return DAG.getNode(ISD::TokenFactor, DL, MVT::Other,
St0, St1);
}
@@ -22604,13 +22603,13 @@ SDValue DAGCombiner::splitMergedValStore(StoreSDNode *ST) {
SDValue Ptr = ST->getBasePtr();
// Lower value store.
SDValue St0 = DAG.getStore(Chain, DL, Lo, Ptr, ST->getPointerInfo(),
- ST->getOriginalAlign(), MMOFlags, AAInfo);
+ ST->getBaseAlign(), MMOFlags, AAInfo);
Ptr =
DAG.getMemBasePlusOffset(Ptr, TypeSize::getFixed(HalfValBitSize / 8), DL);
// Higher value store.
SDValue St1 = DAG.getStore(
St0, DL, Hi, Ptr, ST->getPointerInfo().getWithOffset(HalfValBitSize / 8),
- ST->getOriginalAlign(), MMOFlags, AAInfo);
+ ST->getBaseAlign(), MMOFlags, AAInfo);
return St1;
}
diff --git a/llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp b/llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
index 3e47136edbefc..528c07cc5549d 100644
--- a/llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
@@ -441,7 +441,7 @@ SDValue SelectionDAGLegalize::OptimizeFloatStore(StoreSDNode* ST) {
bitcastToAPInt().zextOrTrunc(32),
SDLoc(CFP), MVT::i32);
return DAG.getStore(Chain, dl, Con, Ptr, ST->getPointerInfo(),
- ST->getOriginalAlign(), MMOFlags, AAInfo);
+ ST->getBaseAlign(), MMOFlags, AAInfo);
}
if (CFP->getValueType(0) == MVT::f64 &&
@@ -451,7 +451,7 @@ SDValue SelectionDAGLegalize::OptimizeFloatStore(StoreSDNode* ST) {
SDValue Con = DAG.getConstant(CFP->getValueAPF().bitcastToAPInt().
zextOrTrunc(64), SDLoc(CFP), MVT::i64);
return DAG.getStore(Chain, dl, Con, Ptr, ST->getPointerInfo(),
- ST->getOriginalAlign(), MMOFlags, AAInfo);
+ ST->getBaseAlign(), MMOFlags, AAInfo);
}
if (TLI.isTypeLegal(MVT::i32) && !ST->isVolatile()) {
@@ -465,11 +465,11 @@ SDValue SelectionDAGLegalize::OptimizeFloatStore(StoreSDNode* ST) {
std::swap(Lo, Hi);
Lo = DAG.getStore(Chain, dl, Lo, Ptr, ST->getPointerInfo(),
- ST->getOriginalAlign(), MMOFlags, AAInfo);
+ ST->getBaseAlign(), MMOFlags, AAInfo);
Ptr = DAG.getMemBasePlusOffset(Ptr, TypeSize::getFixed(4), dl);
Hi = DAG.getStore(Chain, dl, Hi, Ptr,
ST->getPointerInfo().getWithOffset(4),
- ST->getOriginalAlign(), MMOFlags, AAInfo);
+ ST->getBaseAlign(), MMOFlags, AAInfo);
return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Lo, Hi);
}
@@ -525,7 +525,7 @@ void SelectionDAGLegalize::LegalizeStoreOps(SDNode *Node) {
"Can only promote stores to same size type");
Value = DAG.getNode(ISD::BITCAST, dl, NVT, Value);
SDValue Result = DAG.getStore(Chain, dl, Value, Ptr, ST->getPointerInfo(),
- ST->getOriginalAlign(), MMOFlags, AAInfo);
+ ST->getBaseAlign(), MMOFlags, AAInfo);
ReplaceNode(SDValue(Node, 0), Result);
break;
}
@@ -548,7 +548,7 @@ void SelectionDAGLegalize::LegalizeStoreOps(SDNode *Node) {
Value = DAG.getZeroExtendInReg(Value, dl, StVT);
SDValue Result =
DAG.getTruncStore(Chain, dl, Value, Ptr, ST->getPointerInfo(), NVT,
- ST->getOriginalAlign(), MMOFlags, AAInfo);
+ ST->getBaseAlign(), MMOFlags, AAInfo);
ReplaceNode(SDValue(Node, 0), Result);
} else if (!StVT.isVector() && !isPowerOf2_64(StWidth.getFixedValue())) {
// If not storing a power-of-2 number of bits, expand as two stores.
@@ -571,7 +571,7 @@ void SelectionDAGLegalize::LegalizeStoreOps(SDNode *Node) {
// TRUNCSTORE:i24 X -> TRUNCSTORE:i16 X, TRUNCSTORE at +2:i8 (srl X, 16)
// Store the bottom RoundWidth bits.
Lo = DAG.getTruncStore(Chain, dl, Value, Ptr, ST->getPointerInfo(),
- RoundVT, ST->getOriginalAlign(), MMOFlags, AAInfo);
+ RoundVT, ST->getBaseAlign(), MMOFlags, AAInfo);
// Store the remaining ExtraWidth bits.
IncrementSize = RoundWidth / 8;
@@ -583,7 +583,7 @@ void SelectionDAGLegalize::LegalizeStoreOps(SDNode *Node) {
TLI.getShiftAmountTy(Value.getValueType(), DL)));
Hi = DAG.getTruncStore(Chain, dl, Hi, Ptr,
ST->getPointerInfo().getWithOffset(IncrementSize),
- ExtraVT, ST->getOriginalAlign(), MMOFlags, AAInfo);
+ ExtraVT, ST->getBaseAlign(), MMOFlags, AAInfo);
} else {
// Big endian - avoid unaligned stores.
// TRUNCSTORE:i24 X -> TRUNCSTORE:i16 (srl X, 8), TRUNCSTORE at +2:i8 X
@@ -593,7 +593,7 @@ void SelectionDAGLegalize::LegalizeStoreOps(SDNode *Node) {
DAG.getConstant(ExtraWidth, dl,
TLI.getShiftAmountTy(Value.getValueType(), DL)));
Hi = DAG.getTruncStore(Chain, dl, Hi, Ptr, ST->getPointerInfo(), RoundVT,
- ST->getOriginalAlign(), MMOFlags, AAInfo);
+ ST->getBaseAlign(), MMOFlags, AAInfo);
// Store the remaining ExtraWidth bits.
IncrementSize = RoundWidth / 8;
@@ -602,7 +602,7 @@ void SelectionDAGLegalize::LegalizeStoreOps(SDNode *Node) {
Ptr.getValueType()));
Lo = DAG.getTruncStore(Chain, dl, Value, Ptr,
ST->getPointerInfo().getWithOffset(IncrementSize),
- ExtraVT, ST->getOriginalAlign(), MMOFlags, AAInfo);
+ ExtraVT, ST->getBaseAlign(), MMOFlags, AAInfo);
}
// The order of the stores doesn't matter.
@@ -638,16 +638,15 @@ void SelectionDAGLegalize::LegalizeStoreOps(SDNode *Node) {
if (TLI.isTypeLegal(StVT)) {
Value = DAG.getNode(ISD::TRUNCATE, dl, StVT, Value);
Result = DAG.getStore(Chain, dl, Value, Ptr, ST->getPointerInfo(),
- ST->getOriginalAlign(), MMOFlags, AAInfo);
+ ST->getBaseAlign(), MMOFlags, AAInfo);
} else {
// The in-memory type isn't legal. Truncate to the type it would promote
// to, and then do a truncstore.
Value = DAG.getNode(ISD::TRUNCATE, dl,
TLI.getTypeToTransformTo(*DAG.getContext(), StVT),
Value);
- Result =
- DAG.getTruncStore(Chain, dl, Value, Ptr, ST->getPointerInfo(), StVT,
- ST->getOriginalAlign(), MMOFlags, AAInfo);
+ Result = DAG.getTruncStore(Chain, dl, Value, Ptr, ST->getPointerInfo(),
+ StVT, ST->getBaseAlign(), MMOFlags, AAInfo);
}
ReplaceNode(SDValue(Node, 0), Result);
@@ -753,7 +752,7 @@ void SelectionDAGLegalize::LegalizeLoadOps(SDNode *Node) {
SDValue Result = DAG.getExtLoad(NewExtType, dl, Node->getValueType(0),
Chain, Ptr, LD->getPointerInfo(), NVT,
- LD->getOriginalAlign(), MMOFlags, AAInfo);
+ LD->getBaseAlign(), MMOFlags, AAInfo);
Ch = Result.getValue(1); // The chain.
@@ -792,7 +791,7 @@ void SelectionDAGLegalize::LegalizeLoadOps(SDNode *Node) {
// EXTLOAD:i24 -> ZEXTLOAD:i16 | (shl EXTLOAD at +2:i8, 16)
// Load the bottom RoundWidth bits.
Lo = DAG.getExtLoad(ISD::ZEXTLOAD, dl, Node->getValueType(0), Chain, Ptr,
- LD->getPointerInfo(), RoundVT, LD->getOriginalAlign(),
+ LD->getPointerInfo(), RoundVT, LD->getBaseAlign(),
MMOFlags, AAInfo);
// Load the remaining ExtraWidth bits.
@@ -801,7 +800,7 @@ void SelectionDAGLegalize::LegalizeLoadOps(SDNode *Node) {
DAG.getMemBasePlusOffset(Ptr, TypeSize::getFixed(IncrementSize), dl);
Hi = DAG.getExtLoad(ExtType, dl, Node->getValueType(0), Chain, Ptr,
LD->getPointerInfo().getWithOffset(IncrementSize),
- ExtraVT, LD->getOriginalAlign(), MMOFlags, AAInfo);
+ ExtraVT, LD->getBaseAlign(), MMOFlags, AAInfo);
// Build a factor node to remember that this load is independent of
// the other one.
@@ -821,7 +820,7 @@ void SelectionDAGLegalize::LegalizeLoadOps(SDNode *Node) {
// EXTLOAD:i24 -> (shl EXTLOAD:i16, 8) | ZEXTLOAD at +2:i8
// Load the top RoundWidth bits.
Hi = DAG.getExtLoad(ExtType, dl, Node->getValueType(0), Chain, Ptr,
- LD->getPointerInfo(), RoundVT, LD->getOriginalAlign(),
+ LD->getPointerInfo(), RoundVT, LD->getBaseAlign(),
MMOFlags, AAInfo);
// Load the remaining ExtraWidth bits.
@@ -830,7 +829,7 @@ void SelectionDAGLegalize::LegalizeLoadOps(SDNode *Node) {
DAG.getMemBasePlusOffset(Ptr, TypeSize::getFixed(IncrementSize), dl);
Lo = DAG.getExtLoad(ISD::ZEXTLOAD, dl, Node->getValueType(0), Chain, Ptr,
LD->getPointerInfo().getWithOffset(IncrementSize),
- ExtraVT, LD->getOriginalAlign(), MMOFlags, AAInfo);
+ ExtraVT, LD->getBaseAlign(), MMOFlags, AAInfo);
// Build a factor node to remember that this load is independent of
// the other one.
diff --git a/llvm/lib/CodeGen/SelectionDAG/LegalizeFloatTypes.cpp b/llvm/lib/CodeGen/SelectionDAG/LegalizeFloatTypes.cpp
index 08dce6a2fc9e5..41e85521b41ea 100644
--- a/llvm/lib/CodeGen/SelectionDAG/LegalizeFloatTypes.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/LegalizeFloatTypes.cpp
@@ -968,8 +968,8 @@ SDValue DAGTypeLegalizer::SoftenFloatRes_LOAD(SDNode *N) {
if (L->getExtensionType() == ISD::NON_EXTLOAD) {
NewL = DAG.getLoad(L->getAddressingMode(), L->getExtensionType(), NVT, dl,
L->getChain(), L->getBasePtr(), L->getOffset(),
- L->getPointerInfo(), NVT, L->getOriginalAlign(),
- MMOFlags, L->getAAInfo());
+ L->getPointerInfo(), NVT, L->getBaseAlign(), MMOFlags,
+ L->getAAInfo());
// Legalized the chain result - switch anything that used the old chain to
// use the new one.
ReplaceValueWith(SDValue(N, 1), NewL.getValue(1));
@@ -979,8 +979,8 @@ SDValue DAGTypeLegalizer::SoftenFloatRes_LOAD(SDNode *N) {
// Do a non-extending load followed by FP_EXTEND.
NewL = DAG.getLoad(L->getAddressingMode(), ISD::NON_EXTLOAD, L->getMemoryVT(),
dl, L->getChain(), L->getBasePtr(), L->getOffset(),
- L->getPointerInfo(), L->getMemoryVT(),
- L->getOriginalAlign(), MMOFlags, L->getAAInfo());
+ L->getPointerInfo(), L->getMemoryVT(), L->getBaseAlign(),
+ MMOFlags, L->getAAInfo());
// Legalized the chain result - switch anything that used the old chain to
// use the new one.
ReplaceValueWith(SDValue(N, 1), NewL.getValue(1));
@@ -3122,7 +3122,7 @@ SDValue DAGTypeLegalizer::PromoteFloatRes_LOAD(SDNode *N) {
SDValue newL = DAG.getLoad(
L->getAddressingMode(), L->getExtensionType(), IVT, SDLoc(N),
L->getChain(), L->getBasePtr(), L->getOffset(), L->getPointerInfo(), IVT,
- L->getOriginalAlign(), L->getMemOperand()->getFlags(), L->getAAInfo());
+ L->getBaseAlign(), L->getMemOperand()->getFlags(), L->getAAInfo());
// Legalize the chain result by replacing uses of the old value chain with the
// new one
ReplaceValueWith(SDValue(N, 1), newL.getValue(1));
@@ -3551,7 +3551,7 @@ SDValue DAGTypeLegalizer::SoftPromoteHalfRes_LOAD(SDNode *N) {
SDValue NewL =
DAG.getLoad(L->getAddressingMode(), L->getExtensionType(), MVT::i16,
SDLoc(N), L->getChain(), L->getBasePtr(), L->getOffset(),
- L->getPointerInfo(), MVT::i16, L->getOriginalAlign(),
+ L->getPointerInfo(), MVT::i16, L->getBaseAlign(),
L->getMemOperand()->getFlags(), L->getAAInfo());
// Legalize the chain result by replacing uses of the old value chain with the
// new one
diff --git a/llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp b/llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp
index 9ccd6a4d1684c..90af5f2cd8e70 100644
--- a/llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp
@@ -4253,7 +4253,7 @@ void DAGTypeLegalizer::ExpandIntRes_LOAD(LoadSDNode *N,
EVT MemVT = N->getMemoryVT();
Lo = DAG.getExtLoad(ExtType, dl, NVT, Ch, Ptr, N->getPointerInfo(), MemVT,
- N->getOriginalAlign(), MMOFlags, AAInfo);
+ N->getBaseAlign(), MMOFlags, AAInfo);
// Remember the chain.
Ch = Lo.getValue(1);
@@ -4275,8 +4275,8 @@ void DAGTypeLegalizer::ExpandIntRes_LOAD(LoadSDNode *N,
}
} else if (DAG.getDataLayout().isLittleEndian()) {
// Little-endian - low bits are at low addresses.
- Lo = DAG.getLoad(NVT, dl, Ch, Ptr, N->getPointerInfo(),
- N->getOriginalAlign(), MMOFlags, AAInfo);
+ Lo = DAG.getLoad(NVT, dl, Ch, Ptr, N->getPointerInfo(), N->getBaseAlign(),
+ MMOFlags, AAInfo);
unsigned ExcessBits =
N->getMemoryVT().getSizeInBits() - NVT.getSizeInBits();
@@ -4287,7 +4287,7 @@ void DAGTypeLegalizer::ExpandIntRes_LOAD(LoadSDNode *N,
Ptr = DAG.getMemBasePlusOffset(Ptr, TypeSize::getFixed(IncrementSize), dl);
Hi = DAG.getExtLoad(ExtType, dl, NVT, Ch, Ptr,
N->getPointerInfo().getWithOffset(IncrementSize), NEVT,
- N->getOriginalAlign(), MMOFlags, AAInfo);
+ N->getBaseAlign(), MMOFlags, AAInfo);
// Build a factor node to remember that this load is independent of the
// other one.
@@ -4305,7 +4305,7 @@ void DAGTypeLegalizer::ExpandIntRes_LOAD(LoadSDNode *N,
Hi = DAG.getExtLoad(ExtType, dl, NVT, Ch, Ptr, N->getPointerInfo(),
EVT::getIntegerVT(*DAG.getContext(),
MemVT.getSizeInBits() - ExcessBits),
- N->getOriginalAlign(), MMOFlags, AAInfo);
+ N->getBaseAlign(), MMOFlags, AAInfo);
// Increment the pointer to the other half.
Ptr = DAG.getMemBasePlusOffset(Ptr, TypeSize::getFixed(IncrementSize), dl);
@@ -4313,7 +4313,7 @@ void DAGTypeLegalizer::ExpandIntRes_LOAD(LoadSDNode *N,
Lo = DAG.getExtLoad(ISD::ZEXTLOAD, dl, NVT, Ch, Ptr,
N->getPointerInfo().getWithOffset(IncrementSize),
EVT::getIntegerVT(*DAG.getContext(), ExcessBits),
- N->getOriginalAlign(), MMOFlags, AAInfo);
+ N->getBaseAlign(), MMOFlags, AAInfo);
// Build a factor node to remember that this load is independent of the
// other one.
@@ -5808,7 +5808,7 @@ SDValue DAGTypeLegalizer::ExpandIntOp_STORE(StoreSDNode *N, unsigned OpNo) {
if (N->getMemoryVT().bitsLE(NVT)) {
GetExpandedInteger(N->getValue(), Lo, Hi);
return DAG.getTruncStore(Ch, dl, Lo, Ptr, N->getPointerInfo(),
- N->getMemoryVT(), N->getOriginalAlign(), MMOFlags,
+ N->getMemoryVT(), N->getBaseAlign(), MMOFlags,
AAInfo);
}
@@ -5816,8 +5816,8 @@ SDValue DAGTypeLegalizer::ExpandIntOp_STORE(StoreSDNode *N, unsigned OpNo) {
// Little-endian - low bits are at low addresses.
GetExpandedInteger(N->getValue(), Lo, Hi);
- Lo = DAG.getStore(Ch, dl, Lo, Ptr, N->getPointerInfo(),
- N->getOriginalAlign(), MMOFlags, AAInfo);
+ Lo = DAG.getStore(Ch, dl, Lo, Ptr, N->getPointerInfo(), N->getBaseAlign(),
+ MMOFlags, AAInfo);
unsigned ExcessBits =
N->getMemoryVT().getSizeInBits() - NVT.getSizeInBits();
@@ -5828,7 +5828,7 @@ SDValue DAGTypeLegalizer::ExpandIntOp_STORE(StoreSDNode *N, unsigned OpNo) {
Ptr = DAG.getObjectPtrOffset(dl, Ptr, TypeSize::getFixed(IncrementSize));
Hi = DAG.getTruncStore(Ch, dl, Hi, Ptr,
N->getPointerInfo().getWithOffset(IncrementSize),
- NEVT, N->getOriginalAlign(), MMOFlags, AAInfo);
+ NEVT, N->getBaseAlign(), MMOFlags, AAInfo);
return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Lo, Hi);
}
@@ -5857,7 +5857,7 @@ SDValue DAGTypeLegalizer::ExpandIntOp_STORE(StoreSDNode *N, unsigned OpNo) {
// Store both the high bits and maybe some of the low bits.
Hi = DAG.getTruncStore(Ch, dl, Hi, Ptr, N->getPointerInfo(), HiVT,
- N->getOriginalAlign(), MMOFlags, AAInfo);
+ N->getBaseAlign(), MMOFlags, AAInfo);
// Increment the pointer to the other half.
Ptr = DAG.getObjectPtrOffset(dl, Ptr, TypeSize::getFixed(IncrementSize));
@@ -5865,7 +5865,7 @@ SDValue DAGTypeLegalizer::ExpandIntOp_STORE(StoreSDNode *N, unsigned OpNo) {
Lo = DAG.getTruncStore(Ch, dl, Lo, Ptr,
N->getPointerInfo().getWithOffset(IncrementSize),
EVT::getIntegerVT(*DAG.getContext(), ExcessBits),
- N->getOriginalAlign(), MMOFlags, AAInfo);
+ N->getBaseAlign(), MMOFlags, AAInfo);
return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Lo, Hi);
}
diff --git a/llvm/lib/CodeGen/SelectionDAG/LegalizeTypesGeneric.cpp b/llvm/lib/CodeGen/SelectionDAG/LegalizeTypesGeneric.cpp
index 113a3bc0bbea6..88c1af20a321e 100644
--- a/llvm/lib/CodeGen/SelectionDAG/LegalizeTypesGeneric.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/LegalizeTypesGeneric.cpp
@@ -260,15 +260,14 @@ void DAGTypeLegalizer::ExpandRes_NormalLoad(SDNode *N, SDValue &Lo,
assert(NVT.isByteSized() && "Expanded type not byte sized!");
Lo = DAG.getLoad(NVT, dl, Chain, Ptr, LD->getPointerInfo(),
- LD->getOriginalAlign(), LD->getMemOperand()->getFlags(),
- AAInfo);
+ LD->getBaseAlign(), LD->getMemOperand()->getFlags(), AAInfo);
// Increment the pointer to the other half.
unsigned IncrementSize = NVT.getSizeInBits() / 8;
Ptr = DAG.getObjectPtrOffset(dl, Ptr, TypeSize::getFixed(IncrementSize));
- Hi = DAG.getLoad(
- NVT, dl, Chain, Ptr, LD->getPointerInfo().getWithOffset(IncrementSize),
- LD->getOriginalAlign(), LD->getMemOperand()->getFlags(), AAInfo);
+ Hi = DAG.getLoad(NVT, dl, Chain, Ptr,
+ LD->getPointerInfo().getWithOffset(IncrementSize),
+ LD->getBaseAlign(), LD->getMemOperand()->getFlags(), AAInfo);
// Build a factor node to remember that this load is independent of the
// other one.
@@ -495,14 +494,14 @@ SDValue DAGTypeLegalizer::ExpandOp_NormalStore(SDNode *N, unsigned OpNo) {
if (TLI.hasBigEndianPartOrdering(ValueVT, DAG.getDataLayout()))
std::swap(Lo, Hi);
- Lo = DAG.getStore(Chain, dl, Lo, Ptr, St->getPointerInfo(),
- St->getOriginalAlign(), St->getMemOperand()->getFlags(),
- AAInfo);
+ Lo =
+ DAG.getStore(Chain, dl, Lo, Ptr, St->getPointerInfo(), St->getBaseAlign(),
+ St->getMemOperand()->getFlags(), AAInfo);
Ptr = DAG.getObjectPtrOffset(dl, Ptr, TypeSize::getFixed(IncrementSize));
Hi = DAG.getStore(
Chain, dl, Hi, Ptr, St->getPointerInfo().getWithOffset(IncrementSize),
- St->getOriginalAlign(), St->getMemOperand()->getFlags(), AAInfo);
+ St->getBaseAlign(), St->getMemOperand()->getFlags(), AAInfo);
return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Lo, Hi);
}
diff --git a/llvm/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp b/llvm/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp
index 0c0e700f6abca..f9fbd303d5e89 100644
--- a/llvm/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp
@@ -467,7 +467,7 @@ SDValue DAGTypeLegalizer::ScalarizeVecRes_LOAD(LoadSDNode *N) {
N->getValueType(0).getVectorElementType(), SDLoc(N), N->getChain(),
N->getBasePtr(), DAG.getUNDEF(N->getBasePtr().getValueType()),
N->getPointerInfo(), N->getMemoryVT().getVectorElementType(),
- N->getOriginalAlign(), N->getMemOperand()->getFlags(), N->getAAInfo());
+ N->getBaseAlign(), N->getMemOperand()->getFlags(), N->getAAInfo());
// Legalize the chain result - switch anything that used the old chain to
// use the new one.
@@ -1007,13 +1007,12 @@ SDValue DAGTypeLegalizer::ScalarizeVecOp_STORE(StoreSDNode *N, unsigned OpNo){
return DAG.getTruncStore(
N->getChain(), dl, GetScalarizedVector(N->getOperand(1)),
N->getBasePtr(), N->getPointerInfo(),
- N->getMemoryVT().getVectorElementType(), N->getOriginalAlign(),
+ N->getMemoryVT().getVectorElementType(), N->getBaseAlign(),
N->getMemOperand()->getFlags(), N->getAAInfo());
return DAG.getStore(N->getChain(), dl, GetScalarizedVector(N->getOperand(1)),
- N->getBasePtr(), N->getPointerInfo(),
- N->getOriginalAlign(), N->getMemOperand()->getFlags(),
- N->getAAInfo());
+ N->getBasePtr(), N->getPointerInfo(), N->getBaseAlign(),
+ N->getMemOperand()->getFlags(), N->getAAInfo());
}
/// If the value to round is a vector that needs to be scalarized, it must be
@@ -2134,14 +2133,14 @@ void DAGTypeLegalizer::SplitVecRes_LOAD(LoadSDNode *LD, SDValue &Lo,
}
Lo = DAG.getLoad(ISD::UNINDEXED, ExtType, LoVT, dl, Ch, Ptr, Offset,
- LD->getPointerInfo(), LoMemVT, LD->getOriginalAlign(),
- MMOFlags, AAInfo);
+ LD->getPointerInfo(), LoMemVT, LD->getBaseAlign(), MMOFlags,
+ AAInfo);
MachinePointerInfo MPI;
IncrementPointer(LD, LoMemVT, MPI, Ptr);
Hi = DAG.getLoad(ISD::UNINDEXED, ExtType, HiVT, dl, Ch, Ptr, Offset, MPI,
- HiMemVT, LD->getOriginalAlign(), MMOFlags, AAInfo);
+ HiMemVT, LD->getBaseAlign(), MMOFlags, AAInfo);
// Build a factor node to remember that this load is independent of the
// other one.
@@ -2165,7 +2164,7 @@ void DAGTypeLegalizer::SplitVecRes_VP_LOAD(VPLoadSDNode *LD, SDValue &Lo,
SDValue Ptr = LD->getBasePtr();
SDValue Offset = LD->getOffset();
assert(Offset.isUndef() && "Unexpected indexed variable-length load offset");
- Align Alignment = LD->getOriginalAlign();
+ Align Alignment = LD->getBaseAlign();
SDValue Mask = LD->getMask();
SDValue EVL = LD->getVectorLength();
EVT MemoryVT = LD->getMemoryVT();
@@ -2289,7 +2288,7 @@ void DAGTypeLegalizer::SplitVecRes_VP_STRIDED_LOAD(VPStridedLoadSDNode *SLD,
SDValue Ptr =
DAG.getNode(ISD::ADD, DL, PtrVT, SLD->getBasePtr(), Increment);
- Align Alignment = SLD->getOriginalAlign();
+ Align Alignment = SLD->getBaseAlign();
if (LoMemVT.isScalableVector())
Alignment = commonAlignment(
Alignment, LoMemVT.getSizeInBits().getKnownMinValue() / 8);
@@ -2328,7 +2327,7 @@ void DAGTypeLegalizer::SplitVecRes_MLOAD(MaskedLoadSDNode *MLD,
assert(Offset.isUndef() && "Unexpected indexed masked load offset");
SDValue Mask = MLD->getMask();
SDValue PassThru = MLD->getPassThru();
- Align Alignment = MLD->getOriginalAlign();
+ Align Alignment = MLD->getBaseAlign();
ISD::LoadExtType ExtType = MLD->getExtensionType();
// Split Mask operand
@@ -2420,7 +2419,7 @@ void DAGTypeLegalizer::SplitVecRes_Gather(MemSDNode *N, SDValue &Lo,
}();
EVT MemoryVT = N->getMemoryVT();
- Align Alignment = N->getOriginalAlign();
+ Align Alignment = N->getBaseAlign();
// Split Mask operand
SDValue MaskLo, MaskHi;
@@ -3855,7 +3854,7 @@ SDValue DAGTypeLegalizer::SplitVecOp_VP_STORE(VPStoreSDNode *N, unsigned OpNo) {
SDValue Mask = N->getMask();
SDValue EVL = N->getVectorLength();
SDValue Data = N->getValue();
- Align Alignment = N->getOriginalAlign();
+ Align Alignment = N->getBaseAlign();
SDLoc DL(N);
SDValue DataLo, DataHi;
@@ -3979,7 +3978,7 @@ SDValue DAGTypeLegalizer::SplitVecOp_VP_STRIDED_STORE(VPStridedStoreSDNode *N,
DAG.getSExtOrTrunc(N->getStride(), DL, PtrVT));
SDValue Ptr = DAG.getNode(ISD::ADD, DL, PtrVT, N->getBasePtr(), Increment);
- Align Alignment = N->getOriginalAlign();
+ Align Alignment = N->getBaseAlign();
if (LoMemVT.isScalableVector())
Alignment = commonAlignment(Alignment,
LoMemVT.getSizeInBits().getKnownMinValue() / 8);
@@ -4008,7 +4007,7 @@ SDValue DAGTypeLegalizer::SplitVecOp_MSTORE(MaskedStoreSDNode *N,
assert(Offset.isUndef() && "Unexpected indexed masked store offset");
SDValue Mask = N->getMask();
SDValue Data = N->getValue();
- Align Alignment = N->getOriginalAlign();
+ Align Alignment = N->getBaseAlign();
SDLoc DL(N);
SDValue DataLo, DataHi;
@@ -4083,7 +4082,7 @@ SDValue DAGTypeLegalizer::SplitVecOp_Scatter(MemSDNode *N, unsigned OpNo) {
SDValue Ch = N->getChain();
SDValue Ptr = N->getBasePtr();
EVT MemoryVT = N->getMemoryVT();
- Align Alignment = N->getOriginalAlign();
+ Align Alignment = N->getBaseAlign();
SDLoc DL(N);
struct Operands {
SDValue Mask;
@@ -4172,7 +4171,7 @@ SDValue DAGTypeLegalizer::SplitVecOp_STORE(StoreSDNode *N, unsigned OpNo) {
SDValue Ch = N->getChain();
SDValue Ptr = N->getBasePtr();
EVT MemoryVT = N->getMemoryVT();
- Align Alignment = N->getOriginalAlign();
+ Align Alignment = N->getBaseAlign();
MachineMemOperand::Flags MMOFlags = N->getMemOperand()->getFlags();
AAMDNodes AAInfo = N->getAAInfo();
SDValue Lo, Hi;
@@ -7876,7 +7875,7 @@ SDValue DAGTypeLegalizer::GenWidenVectorLoads(SmallVectorImpl<SDValue> &LdChain,
}
SDValue LdOp = DAG.getLoad(*FirstVT, dl, Chain, BasePtr, LD->getPointerInfo(),
- LD->getOriginalAlign(), MMOFlags, AAInfo);
+ LD->getBaseAlign(), MMOFlags, AAInfo);
LdChain.push_back(LdOp.getValue(1));
// Check if we can load the element with one instruction.
@@ -7917,7 +7916,7 @@ SDValue DAGTypeLegalizer::GenWidenVectorLoads(SmallVectorImpl<SDValue> &LdChain,
for (EVT MemVT : MemVTs) {
Align NewAlign = ScaledOffset == 0
- ? LD->getOriginalAlign()
+ ? LD->getBaseAlign()
: commonAlignment(LD->getAlign(), ScaledOffset);
SDValue L =
DAG.getLoad(MemVT, dl, Chain, BasePtr, MPI, NewAlign, MMOFlags, AAInfo);
@@ -8027,7 +8026,7 @@ DAGTypeLegalizer::GenWidenVectorExtLoads(SmallVectorImpl<SDValue> &LdChain,
unsigned Increment = LdEltVT.getSizeInBits() / 8;
Ops[0] =
DAG.getExtLoad(ExtType, dl, EltVT, Chain, BasePtr, LD->getPointerInfo(),
- LdEltVT, LD->getOriginalAlign(), MMOFlags, AAInfo);
+ LdEltVT, LD->getBaseAlign(), MMOFlags, AAInfo);
LdChain.push_back(Ops[0].getValue(1));
unsigned i = 0, Offset = Increment;
for (i=1; i < NumElts; ++i, Offset += Increment) {
@@ -8035,7 +8034,7 @@ DAGTypeLegalizer::GenWidenVectorExtLoads(SmallVectorImpl<SDValue> &LdChain,
DAG.getObjectPtrOffset(dl, BasePtr, TypeSize::getFixed(Offset));
Ops[i] = DAG.getExtLoad(ExtType, dl, EltVT, Chain, NewBasePtr,
LD->getPointerInfo().getWithOffset(Offset), LdEltVT,
- LD->getOriginalAlign(), MMOFlags, AAInfo);
+ LD->getBaseAlign(), MMOFlags, AAInfo);
LdChain.push_back(Ops[i].getValue(1));
}
@@ -8103,7 +8102,7 @@ bool DAGTypeLegalizer::GenWidenVectorStores(SmallVectorImpl<SDValue> &StChain,
unsigned NumVTElts = NewVT.getVectorMinNumElements();
do {
Align NewAlign = ScaledOffset == 0
- ? ST->getOriginalAlign()
+ ? ST->getBaseAlign()
: commonAlignment(ST->getAlign(), ScaledOffset);
SDValue EOp = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, NewVT, ValOp,
DAG.getVectorIdxConstant(Idx, dl));
@@ -8125,9 +8124,8 @@ bool DAGTypeLegalizer::GenWidenVectorStores(SmallVectorImpl<SDValue> &StChain,
do {
SDValue EOp = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, NewVT, VecOp,
DAG.getVectorIdxConstant(Idx++, dl));
- SDValue PartStore =
- DAG.getStore(Chain, dl, EOp, BasePtr, MPI, ST->getOriginalAlign(),
- MMOFlags, AAInfo);
+ SDValue PartStore = DAG.getStore(Chain, dl, EOp, BasePtr, MPI,
+ ST->getBaseAlign(), MMOFlags, AAInfo);
StChain.push_back(PartStore);
IncrementPointer(cast<StoreSDNode>(PartStore), NewVT, MPI, BasePtr);
diff --git a/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp b/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp
index f17d6a2787889..da999b5057d49 100644
--- a/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp
@@ -4766,7 +4766,7 @@ SDValue TargetLowering::SimplifySetCC(EVT VT, SDValue N0, SDValue N1,
SDValue NewLoad =
DAG.getLoad(newVT, dl, Lod->getChain(), Ptr,
Lod->getPointerInfo().getWithOffset(bestOffset),
- Lod->getOriginalAlign());
+ Lod->getBaseAlign());
SDValue And =
DAG.getNode(ISD::AND, dl, newVT, NewLoad,
DAG.getConstant(bestMask.trunc(bestWidth), dl, newVT));
@@ -10007,7 +10007,7 @@ TargetLowering::scalarizeVectorLoad(LoadSDNode *LD,
// the codegen worse.
SDValue Load =
DAG.getExtLoad(ISD::EXTLOAD, SL, LoadVT, Chain, BasePTR,
- LD->getPointerInfo(), SrcIntVT, LD->getOriginalAlign(),
+ LD->getPointerInfo(), SrcIntVT, LD->getBaseAlign(),
LD->getMemOperand()->getFlags(), LD->getAAInfo());
SmallVector<SDValue, 8> Vals;
@@ -10040,11 +10040,10 @@ TargetLowering::scalarizeVectorLoad(LoadSDNode *LD,
SmallVector<SDValue, 8> LoadChains;
for (unsigned Idx = 0; Idx < NumElem; ++Idx) {
- SDValue ScalarLoad =
- DAG.getExtLoad(ExtType, SL, DstEltVT, Chain, BasePTR,
- LD->getPointerInfo().getWithOffset(Idx * Stride),
- SrcEltVT, LD->getOriginalAlign(),
- LD->getMemOperand()->getFlags(), LD->getAAInfo());
+ SDValue ScalarLoad = DAG.getExtLoad(
+ ExtType, SL, DstEltVT, Chain, BasePTR,
+ LD->getPointerInfo().getWithOffset(Idx * Stride), SrcEltVT,
+ LD->getBaseAlign(), LD->getMemOperand()->getFlags(), LD->getAAInfo());
BasePTR = DAG.getObjectPtrOffset(SL, BasePTR, TypeSize::getFixed(Stride));
@@ -10106,7 +10105,7 @@ SDValue TargetLowering::scalarizeVectorStore(StoreSDNode *ST,
}
return DAG.getStore(Chain, SL, CurrVal, BasePtr, ST->getPointerInfo(),
- ST->getOriginalAlign(), ST->getMemOperand()->getFlags(),
+ ST->getBaseAlign(), ST->getMemOperand()->getFlags(),
ST->getAAInfo());
}
@@ -10126,7 +10125,7 @@ SDValue TargetLowering::scalarizeVectorStore(StoreSDNode *ST,
// This scalar TruncStore may be illegal, but we legalize it later.
SDValue Store = DAG.getTruncStore(
Chain, SL, Elt, Ptr, ST->getPointerInfo().getWithOffset(Idx * Stride),
- MemSclVT, ST->getOriginalAlign(), ST->getMemOperand()->getFlags(),
+ MemSclVT, ST->getBaseAlign(), ST->getMemOperand()->getFlags(),
ST->getAAInfo());
Stores.push_back(Store);
@@ -10192,8 +10191,7 @@ TargetLowering::expandUnalignedLoad(LoadSDNode *LD, SelectionDAG &DAG) const {
// Load one integer register's worth from the original location.
SDValue Load = DAG.getLoad(
RegVT, dl, Chain, Ptr, LD->getPointerInfo().getWithOffset(Offset),
- LD->getOriginalAlign(), LD->getMemOperand()->getFlags(),
- LD->getAAInfo());
+ LD->getBaseAlign(), LD->getMemOperand()->getFlags(), LD->getAAInfo());
// Follow the load with a store to the stack slot. Remember the store.
Stores.push_back(DAG.getStore(
Load.getValue(1), dl, Load, StackPtr,
@@ -10208,11 +10206,10 @@ TargetLowering::expandUnalignedLoad(LoadSDNode *LD, SelectionDAG &DAG) const {
// The last copy may be partial. Do an extending load.
EVT MemVT = EVT::getIntegerVT(*DAG.getContext(),
8 * (LoadedBytes - Offset));
- SDValue Load =
- DAG.getExtLoad(ISD::EXTLOAD, dl, RegVT, Chain, Ptr,
- LD->getPointerInfo().getWithOffset(Offset), MemVT,
- LD->getOriginalAlign(), LD->getMemOperand()->getFlags(),
- LD->getAAInfo());
+ SDValue Load = DAG.getExtLoad(
+ ISD::EXTLOAD, dl, RegVT, Chain, Ptr,
+ LD->getPointerInfo().getWithOffset(Offset), MemVT, LD->getBaseAlign(),
+ LD->getMemOperand()->getFlags(), LD->getAAInfo());
// Follow the load with a store to the stack slot. Remember the store.
// On big-endian machines this requires a truncating store to ensure
// that the bits end up in the right place.
@@ -10242,7 +10239,7 @@ TargetLowering::expandUnalignedLoad(LoadSDNode *LD, SelectionDAG &DAG) const {
NewLoadedVT = EVT::getIntegerVT(*DAG.getContext(), NumBits/2);
NumBits >>= 1;
- Align Alignment = LD->getOriginalAlign();
+ Align Alignment = LD->getBaseAlign();
unsigned IncrementSize = NumBits / 8;
ISD::LoadExtType HiExtType = LD->getExtensionType();
@@ -10293,7 +10290,7 @@ SDValue TargetLowering::expandUnalignedStore(StoreSDNode *ST,
SDValue Ptr = ST->getBasePtr();
SDValue Val = ST->getValue();
EVT VT = Val.getValueType();
- Align Alignment = ST->getOriginalAlign();
+ Align Alignment = ST->getBaseAlign();
auto &MF = DAG.getMachineFunction();
EVT StoreMemVT = ST->getMemoryVT();
@@ -10350,7 +10347,7 @@ SDValue TargetLowering::expandUnalignedStore(StoreSDNode *ST,
// Store it to the final location. Remember the store.
Stores.push_back(DAG.getStore(Load.getValue(1), dl, Load, Ptr,
ST->getPointerInfo().getWithOffset(Offset),
- ST->getOriginalAlign(),
+ ST->getBaseAlign(),
ST->getMemOperand()->getFlags()));
// Increment the pointers.
Offset += RegBytes;
@@ -10369,11 +10366,10 @@ SDValue TargetLowering::expandUnalignedStore(StoreSDNode *ST,
ISD::EXTLOAD, dl, RegVT, Store, StackPtr,
MachinePointerInfo::getFixedStack(MF, FrameIndex, Offset), LoadMemVT);
- Stores.push_back(
- DAG.getTruncStore(Load.getValue(1), dl, Load, Ptr,
- ST->getPointerInfo().getWithOffset(Offset), LoadMemVT,
- ST->getOriginalAlign(),
- ST->getMemOperand()->getFlags(), ST->getAAInfo()));
+ Stores.push_back(DAG.getTruncStore(
+ Load.getValue(1), dl, Load, Ptr,
+ ST->getPointerInfo().getWithOffset(Offset), LoadMemVT,
+ ST->getBaseAlign(), ST->getMemOperand()->getFlags(), ST->getAAInfo()));
// The order of the stores doesn't matter - say it with a TokenFactor.
SDValue Result = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Stores);
return Result;
diff --git a/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp b/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
index c7858e4106358..acdb3f98b081b 100644
--- a/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
+++ b/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
@@ -7028,7 +7028,7 @@ SDValue AArch64TargetLowering::LowerSTORE(SDValue Op,
SDValue Ptr = DAG.getNode(ISD::ADD, Dl, PtrVT, Base,
DAG.getConstant(i * 8, Dl, PtrVT));
Chain = DAG.getStore(Chain, Dl, Part, Ptr, StoreNode->getPointerInfo(),
- StoreNode->getOriginalAlign());
+ StoreNode->getBaseAlign());
}
return Chain;
}
@@ -7082,9 +7082,9 @@ SDValue AArch64TargetLowering::LowerLOAD(SDValue Op,
for (unsigned i = 0; i < 8; i++) {
SDValue Ptr = DAG.getNode(ISD::ADD, DL, PtrVT, Base,
DAG.getConstant(i * 8, DL, PtrVT));
- SDValue Part = DAG.getLoad(MVT::i64, DL, Chain, Ptr,
- LoadNode->getPointerInfo(),
- LoadNode->getOriginalAlign());
+ SDValue Part =
+ DAG.getLoad(MVT::i64, DL, Chain, Ptr, LoadNode->getPointerInfo(),
+ LoadNode->getBaseAlign());
Ops.push_back(Part);
Chain = SDValue(Part.getNode(), 1);
}
@@ -21377,7 +21377,7 @@ static SDValue performExtBinopLoadFold(SDNode *N, SelectionDAG &DAG) {
for (const auto &[L0, L1] : zip(Loads0, Loads1)) {
SDValue Load = DAG.getLoad(DLoadVT, SDLoc(L0), L0->getChain(),
L0->getBasePtr(), L0->getPointerInfo(),
- L0->getOriginalAlign());
+ L0->getBaseAlign());
DAG.makeEquivalentMemoryOrdering(L0, Load.getValue(1));
DAG.makeEquivalentMemoryOrdering(L1, Load.getValue(1));
NewLoads.push_back(Load);
@@ -23580,7 +23580,7 @@ static SDValue foldTruncStoreOfExt(SelectionDAG &DAG, SDNode *N) {
static SDValue combineV3I8LoadExt(LoadSDNode *LD, SelectionDAG &DAG) {
EVT MemVT = LD->getMemoryVT();
if (MemVT != EVT::getVectorVT(*DAG.getContext(), MVT::i8, 3) ||
- LD->getOriginalAlign() >= 4)
+ LD->getBaseAlign() >= 4)
return SDValue();
SDLoc DL(LD);
@@ -23642,7 +23642,7 @@ static SDValue performLOADCombine(SDNode *N,
DAG.getAddrSpaceCast(DL, PtrVT, LD->getBasePtr(), AddrSpace, 0);
return DAG.getExtLoad(LD->getExtensionType(), DL, RegVT, LD->getChain(),
Cast, LD->getPointerInfo(), MemVT,
- LD->getOriginalAlign(),
+ LD->getBaseAlign(),
LD->getMemOperand()->getFlags());
}
}
@@ -23953,8 +23953,8 @@ static SDValue performSTORECombine(SDNode *N,
if (PtrVT != Ptr.getSimpleValueType()) {
SDValue Cast = DAG.getAddrSpaceCast(DL, PtrVT, Ptr, AddrSpace, 0);
return DAG.getStore(Chain, DL, Value, Cast, ST->getPointerInfo(),
- ST->getOriginalAlign(),
- ST->getMemOperand()->getFlags(), ST->getAAInfo());
+ ST->getBaseAlign(), ST->getMemOperand()->getFlags(),
+ ST->getAAInfo());
}
}
diff --git a/llvm/lib/Target/ARM/ARMISelLowering.cpp b/llvm/lib/Target/ARM/ARMISelLowering.cpp
index c9d96f85dd370..afbf1b4c55e70 100644
--- a/llvm/lib/Target/ARM/ARMISelLowering.cpp
+++ b/llvm/lib/Target/ARM/ARMISelLowering.cpp
@@ -16772,7 +16772,7 @@ static SDValue PerformSplittingToNarrowingStores(StoreSDNode *St,
// Details about the old store
SDValue Ch = St->getChain();
SDValue BasePtr = St->getBasePtr();
- Align Alignment = St->getOriginalAlign();
+ Align Alignment = St->getBaseAlign();
MachineMemOperand::Flags MMOFlags = St->getMemOperand()->getFlags();
AAMDNodes AAInfo = St->getAAInfo();
@@ -16823,7 +16823,7 @@ static SDValue PerformSplittingMVETruncToNarrowingStores(StoreSDNode *St,
// Details about the old store
SDValue Ch = St->getChain();
SDValue BasePtr = St->getBasePtr();
- Align Alignment = St->getOriginalAlign();
+ Align Alignment = St->getBaseAlign();
MachineMemOperand::Flags MMOFlags = St->getMemOperand()->getFlags();
AAMDNodes AAInfo = St->getAAInfo();
@@ -16871,7 +16871,7 @@ static SDValue PerformExtractFpToIntStores(StoreSDNode *St, SelectionDAG &DAG) {
// Create a new integer store to replace the existing floating point version.
SDValue Ch = St->getChain();
SDValue BasePtr = St->getBasePtr();
- Align Alignment = St->getOriginalAlign();
+ Align Alignment = St->getBaseAlign();
MachineMemOperand::Flags MMOFlags = St->getMemOperand()->getFlags();
AAMDNodes AAInfo = St->getAAInfo();
EVT NewToVT = EVT::getIntegerVT(C, VT.getSizeInBits());
@@ -16922,7 +16922,7 @@ static SDValue PerformSTORECombine(SDNode *N,
SDValue BasePtr = St->getBasePtr();
SDValue NewST1 = DAG.getStore(
St->getChain(), DL, StVal.getNode()->getOperand(isBigEndian ? 1 : 0),
- BasePtr, St->getPointerInfo(), St->getOriginalAlign(),
+ BasePtr, St->getPointerInfo(), St->getBaseAlign(),
St->getMemOperand()->getFlags());
SDValue OffsetPtr = DAG.getNode(ISD::ADD, DL, MVT::i32, BasePtr,
@@ -16930,8 +16930,7 @@ static SDValue PerformSTORECombine(SDNode *N,
return DAG.getStore(NewST1.getValue(0), DL,
StVal.getNode()->getOperand(isBigEndian ? 0 : 1),
OffsetPtr, St->getPointerInfo().getWithOffset(4),
- St->getOriginalAlign(),
- St->getMemOperand()->getFlags());
+ St->getBaseAlign(), St->getMemOperand()->getFlags());
}
if (StVal.getValueType() == MVT::i64 &&
@@ -17913,7 +17912,7 @@ static SDValue PerformSplittingToWideningLoad(SDNode *N, SelectionDAG &DAG) {
// Details about the old load
SDValue Ch = LD->getChain();
SDValue BasePtr = LD->getBasePtr();
- Align Alignment = LD->getOriginalAlign();
+ Align Alignment = LD->getBaseAlign();
MachineMemOperand::Flags MMOFlags = LD->getMemOperand()->getFlags();
AAMDNodes AAInfo = LD->getAAInfo();
@@ -18819,7 +18818,7 @@ static SDValue PerformSplittingMVEEXTToWideningLoad(SDNode *N,
// Details about the old load
SDValue Ch = LD->getChain();
SDValue BasePtr = LD->getBasePtr();
- Align Alignment = LD->getOriginalAlign();
+ Align Alignment = LD->getBaseAlign();
MachineMemOperand::Flags MMOFlags = LD->getMemOperand()->getFlags();
AAMDNodes AAInfo = LD->getAAInfo();
diff --git a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
index fae2cda13863d..c5dca352078ae 100644
--- a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
+++ b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
@@ -5684,12 +5684,11 @@ static SDValue lowerVECTOR_SHUFFLE(SDValue Op, SelectionDAG &DAG,
if (SVT.isFloatingPoint())
V = DAG.getLoad(SVT, DL, Ld->getChain(), NewAddr,
Ld->getPointerInfo().getWithOffset(Offset),
- Ld->getOriginalAlign(),
- Ld->getMemOperand()->getFlags());
+ Ld->getBaseAlign(), Ld->getMemOperand()->getFlags());
else
V = DAG.getExtLoad(ISD::EXTLOAD, DL, XLenVT, Ld->getChain(), NewAddr,
Ld->getPointerInfo().getWithOffset(Offset), SVT,
- Ld->getOriginalAlign(),
+ Ld->getBaseAlign(),
Ld->getMemOperand()->getFlags());
DAG.makeEquivalentMemoryOrdering(Ld, V);
@@ -6398,7 +6397,7 @@ SDValue RISCVTargetLowering::expandUnalignedRVVLoad(SDValue Op,
assert(NewVT.isValid() &&
"Expecting equally-sized RVV vector types to be legal");
SDValue L = DAG.getLoad(NewVT, DL, Load->getChain(), Load->getBasePtr(),
- Load->getPointerInfo(), Load->getOriginalAlign(),
+ Load->getPointerInfo(), Load->getBaseAlign(),
Load->getMemOperand()->getFlags());
return DAG.getMergeValues({DAG.getBitcast(VT, L), L.getValue(1)}, DL);
}
@@ -6430,7 +6429,7 @@ SDValue RISCVTargetLowering::expandUnalignedRVVStore(SDValue Op,
"Expecting equally-sized RVV vector types to be legal");
StoredVal = DAG.getBitcast(NewVT, StoredVal);
return DAG.getStore(Store->getChain(), DL, StoredVal, Store->getBasePtr(),
- Store->getPointerInfo(), Store->getOriginalAlign(),
+ Store->getPointerInfo(), Store->getBaseAlign(),
Store->getMemOperand()->getFlags());
}
@@ -7869,7 +7868,7 @@ SDValue RISCVTargetLowering::LowerOperation(SDValue Op,
StoredVal, DAG.getVectorIdxConstant(i, DL));
Ret = DAG.getStore(Chain, DL, Extract, BasePtr,
MachinePointerInfo(Store->getAddressSpace()),
- Store->getOriginalAlign(),
+ Store->getBaseAlign(),
Store->getMemOperand()->getFlags());
Chain = Ret.getValue(0);
BasePtr = DAG.getNode(ISD::ADD, DL, XLenVT, BasePtr, VROffset, Flag);
@@ -19895,7 +19894,7 @@ SDValue RISCVTargetLowering::PerformDAGCombine(SDNode *N,
NewVT, *Store->getMemOperand())) {
SDValue NewV = DAG.getConstant(NewC, DL, NewVT);
return DAG.getStore(Chain, DL, NewV, Store->getBasePtr(),
- Store->getPointerInfo(), Store->getOriginalAlign(),
+ Store->getPointerInfo(), Store->getBaseAlign(),
Store->getMemOperand()->getFlags());
}
}
@@ -19915,10 +19914,10 @@ SDValue RISCVTargetLowering::PerformDAGCombine(SDNode *N,
allowsMemoryAccessForAlignment(*DAG.getContext(), DAG.getDataLayout(),
NewVT, *L->getMemOperand())) {
SDValue NewL = DAG.getLoad(NewVT, DL, L->getChain(), L->getBasePtr(),
- L->getPointerInfo(), L->getOriginalAlign(),
+ L->getPointerInfo(), L->getBaseAlign(),
L->getMemOperand()->getFlags());
return DAG.getStore(Chain, DL, NewL, Store->getBasePtr(),
- Store->getPointerInfo(), Store->getOriginalAlign(),
+ Store->getPointerInfo(), Store->getBaseAlign(),
Store->getMemOperand()->getFlags());
}
}
diff --git a/llvm/lib/Target/Sparc/SparcISelLowering.cpp b/llvm/lib/Target/Sparc/SparcISelLowering.cpp
index b83aecffe779c..f8141c8daf6e7 100644
--- a/llvm/lib/Target/Sparc/SparcISelLowering.cpp
+++ b/llvm/lib/Target/Sparc/SparcISelLowering.cpp
@@ -2952,7 +2952,7 @@ static SDValue LowerF128Load(SDValue Op, SelectionDAG &DAG)
LoadSDNode *LdNode = cast<LoadSDNode>(Op.getNode());
assert(LdNode->getOffset().isUndef() && "Unexpected node type");
- Align Alignment = commonAlignment(LdNode->getOriginalAlign(), 8);
+ Align Alignment = commonAlignment(LdNode->getBaseAlign(), 8);
SDValue Hi64 =
DAG.getLoad(MVT::f64, dl, LdNode->getChain(), LdNode->getBasePtr(),
@@ -3018,7 +3018,7 @@ static SDValue LowerF128Store(SDValue Op, SelectionDAG &DAG) {
StNode->getValue(),
SubRegOdd);
- Align Alignment = commonAlignment(StNode->getOriginalAlign(), 8);
+ Align Alignment = commonAlignment(StNode->getBaseAlign(), 8);
SDValue OutChains[2];
OutChains[0] =
@@ -3050,8 +3050,7 @@ static SDValue LowerSTORE(SDValue Op, SelectionDAG &DAG)
SDValue Val = DAG.getNode(ISD::BITCAST, dl, MVT::v2i32, St->getValue());
SDValue Chain = DAG.getStore(
St->getChain(), dl, Val, St->getBasePtr(), St->getPointerInfo(),
- St->getOriginalAlign(), St->getMemOperand()->getFlags(),
- St->getAAInfo());
+ St->getBaseAlign(), St->getMemOperand()->getFlags(), St->getAAInfo());
return Chain;
}
@@ -3537,9 +3536,8 @@ void SparcTargetLowering::ReplaceNodeResults(SDNode *N,
SDLoc dl(N);
SDValue LoadRes = DAG.getExtLoad(
Ld->getExtensionType(), dl, MVT::v2i32, Ld->getChain(),
- Ld->getBasePtr(), Ld->getPointerInfo(), MVT::v2i32,
- Ld->getOriginalAlign(), Ld->getMemOperand()->getFlags(),
- Ld->getAAInfo());
+ Ld->getBasePtr(), Ld->getPointerInfo(), MVT::v2i32, Ld->getBaseAlign(),
+ Ld->getMemOperand()->getFlags(), Ld->getAAInfo());
SDValue Res = DAG.getNode(ISD::BITCAST, dl, MVT::i64, LoadRes);
Results.push_back(Res);
diff --git a/llvm/lib/Target/SystemZ/SystemZISelLowering.cpp b/llvm/lib/Target/SystemZ/SystemZISelLowering.cpp
index db8b2bdb62077..8eb2c84be9b60 100644
--- a/llvm/lib/Target/SystemZ/SystemZISelLowering.cpp
+++ b/llvm/lib/Target/SystemZ/SystemZISelLowering.cpp
@@ -6930,10 +6930,9 @@ SDValue SystemZTargetLowering::lowerLoadF16(SDValue Op,
} else {
LoadSDNode *Ld = cast<LoadSDNode>(Op.getNode());
assert(EVT(RegVT) == Ld->getMemoryVT() && "Unhandled f16 load");
- NewLd =
- DAG.getExtLoad(ISD::EXTLOAD, DL, MVT::i64, Ld->getChain(),
- Ld->getBasePtr(), Ld->getPointerInfo(), MVT::i16,
- Ld->getOriginalAlign(), Ld->getMemOperand()->getFlags());
+ NewLd = DAG.getExtLoad(ISD::EXTLOAD, DL, MVT::i64, Ld->getChain(),
+ Ld->getBasePtr(), Ld->getPointerInfo(), MVT::i16,
+ Ld->getBaseAlign(), Ld->getMemOperand()->getFlags());
}
SDValue F16Val = convertToF16(NewLd, DAG);
return DAG.getMergeValues({F16Val, NewLd.getValue(1)}, DL);
@@ -7949,7 +7948,7 @@ SDValue SystemZTargetLowering::combineLOAD(
if (HiPart) {
SDValue EltLoad = DAG.getLoad(
HiPart->getValueType(0), DL, LD->getChain(), LD->getBasePtr(),
- LD->getPointerInfo(), LD->getOriginalAlign(),
+ LD->getPointerInfo(), LD->getBaseAlign(),
LD->getMemOperand()->getFlags(), LD->getAAInfo());
DCI.CombineTo(HiPart, EltLoad, true);
@@ -7959,7 +7958,7 @@ SDValue SystemZTargetLowering::combineLOAD(
SDValue EltLoad = DAG.getLoad(
LoPart->getValueType(0), DL, LD->getChain(),
DAG.getObjectPtrOffset(DL, LD->getBasePtr(), TypeSize::getFixed(8)),
- LD->getPointerInfo().getWithOffset(8), LD->getOriginalAlign(),
+ LD->getPointerInfo().getWithOffset(8), LD->getBaseAlign(),
LD->getMemOperand()->getFlags(), LD->getAAInfo());
DCI.CombineTo(LoPart, EltLoad, true);
@@ -8109,7 +8108,7 @@ SDValue SystemZTargetLowering::combineSTORE(
SDValue AddrSpaceCast = DAG.getAddrSpaceCast(DL, PtrVT, SN->getBasePtr(),
SYSTEMZAS::PTR32, 0);
return DAG.getStore(SN->getChain(), DL, SN->getValue(), AddrSpaceCast,
- SN->getPointerInfo(), SN->getOriginalAlign(),
+ SN->getPointerInfo(), SN->getBaseAlign(),
SN->getMemOperand()->getFlags(), SN->getAAInfo());
}
}
@@ -8183,17 +8182,14 @@ SDValue SystemZTargetLowering::combineSTORE(
if ((MemVT == MVT::i128 && isI128MovedFromParts(Op1, LoPart, HiPart)) ||
(MemVT == MVT::f128 && isF128MovedFromParts(Op1, LoPart, HiPart))) {
SDLoc DL(SN);
- SDValue Chain0 =
- DAG.getStore(SN->getChain(), DL, HiPart, SN->getBasePtr(),
- SN->getPointerInfo(), SN->getOriginalAlign(),
- SN->getMemOperand()->getFlags(), SN->getAAInfo());
- SDValue Chain1 =
- DAG.getStore(SN->getChain(), DL, LoPart,
- DAG.getObjectPtrOffset(DL, SN->getBasePtr(),
- TypeSize::getFixed(8)),
- SN->getPointerInfo().getWithOffset(8),
- SN->getOriginalAlign(),
- SN->getMemOperand()->getFlags(), SN->getAAInfo());
+ SDValue Chain0 = DAG.getStore(
+ SN->getChain(), DL, HiPart, SN->getBasePtr(), SN->getPointerInfo(),
+ SN->getBaseAlign(), SN->getMemOperand()->getFlags(), SN->getAAInfo());
+ SDValue Chain1 = DAG.getStore(
+ SN->getChain(), DL, LoPart,
+ DAG.getObjectPtrOffset(DL, SN->getBasePtr(), TypeSize::getFixed(8)),
+ SN->getPointerInfo().getWithOffset(8), SN->getBaseAlign(),
+ SN->getMemOperand()->getFlags(), SN->getAAInfo());
return DAG.getNode(ISD::TokenFactor, DL, MVT::Other, Chain0, Chain1);
}
diff --git a/llvm/lib/Target/X86/X86ISelLowering.cpp b/llvm/lib/Target/X86/X86ISelLowering.cpp
index 70d44ad96cd64..6b4b4beb97ca5 100644
--- a/llvm/lib/Target/X86/X86ISelLowering.cpp
+++ b/llvm/lib/Target/X86/X86ISelLowering.cpp
@@ -7349,8 +7349,7 @@ static SDValue EltsFromConsecutiveLoads(EVT VT, ArrayRef<SDValue> Elts,
"Cannot merge volatile or atomic loads.");
SDValue NewLd =
DAG.getLoad(VT, DL, LDBase->getChain(), LDBase->getBasePtr(),
- LDBase->getPointerInfo(), LDBase->getOriginalAlign(),
- MMOFlags);
+ LDBase->getPointerInfo(), LDBase->getBaseAlign(), MMOFlags);
for (auto *LD : Loads)
if (LD)
DAG.makeEquivalentMemoryOrdering(LD, NewLd);
@@ -7438,7 +7437,7 @@ static SDValue EltsFromConsecutiveLoads(EVT VT, ArrayRef<SDValue> Elts,
SDValue Ops[] = { LDBase->getChain(), LDBase->getBasePtr() };
SDValue ResNode = DAG.getMemIntrinsicNode(
X86ISD::VZEXT_LOAD, DL, Tys, Ops, VecSVT, LDBase->getPointerInfo(),
- LDBase->getOriginalAlign(), MachineMemOperand::MOLoad);
+ LDBase->getBaseAlign(), MachineMemOperand::MOLoad);
for (auto *LD : Loads)
if (LD)
DAG.makeEquivalentMemoryOrdering(LD, ResNode);
@@ -25372,12 +25371,11 @@ static SDValue splitVectorStore(StoreSDNode *Store, SelectionDAG &DAG) {
DAG.getMemBasePlusOffset(Ptr0, TypeSize::getFixed(HalfOffset), DL);
SDValue Ch0 =
DAG.getStore(Store->getChain(), DL, Value0, Ptr0, Store->getPointerInfo(),
- Store->getOriginalAlign(),
- Store->getMemOperand()->getFlags());
- SDValue Ch1 = DAG.getStore(Store->getChain(), DL, Value1, Ptr1,
- Store->getPointerInfo().getWithOffset(HalfOffset),
- Store->getOriginalAlign(),
- Store->getMemOperand()->getFlags());
+ Store->getBaseAlign(), Store->getMemOperand()->getFlags());
+ SDValue Ch1 =
+ DAG.getStore(Store->getChain(), DL, Value1, Ptr1,
+ Store->getPointerInfo().getWithOffset(HalfOffset),
+ Store->getBaseAlign(), Store->getMemOperand()->getFlags());
return DAG.getNode(ISD::TokenFactor, DL, MVT::Other, Ch0, Ch1);
}
@@ -25408,10 +25406,10 @@ static SDValue scalarizeVectorStore(StoreSDNode *Store, MVT StoreVT,
TypeSize::getFixed(Offset), DL);
SDValue Scl = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, StoreSVT, StoredVal,
DAG.getVectorIdxConstant(i, DL));
- SDValue Ch = DAG.getStore(Store->getChain(), DL, Scl, Ptr,
- Store->getPointerInfo().getWithOffset(Offset),
- Store->getOriginalAlign(),
- Store->getMemOperand()->getFlags());
+ SDValue Ch =
+ DAG.getStore(Store->getChain(), DL, Scl, Ptr,
+ Store->getPointerInfo().getWithOffset(Offset),
+ Store->getBaseAlign(), Store->getMemOperand()->getFlags());
Stores.push_back(Ch);
}
return DAG.getNode(ISD::TokenFactor, DL, MVT::Other, Stores);
@@ -25444,7 +25442,7 @@ static SDValue LowerStore(SDValue Op, const X86Subtarget &Subtarget,
StoredVal, dl, EVT::getIntegerVT(*DAG.getContext(), NumElts));
return DAG.getStore(St->getChain(), dl, StoredVal, St->getBasePtr(),
- St->getPointerInfo(), St->getOriginalAlign(),
+ St->getPointerInfo(), St->getBaseAlign(),
St->getMemOperand()->getFlags());
}
@@ -25487,7 +25485,7 @@ static SDValue LowerStore(SDValue Op, const X86Subtarget &Subtarget,
DAG.getVectorIdxConstant(0, dl));
return DAG.getStore(St->getChain(), dl, StoredVal, St->getBasePtr(),
- St->getPointerInfo(), St->getOriginalAlign(),
+ St->getPointerInfo(), St->getBaseAlign(),
St->getMemOperand()->getFlags());
}
assert(Subtarget.hasSSE1() && "Expected SSE");
@@ -25522,7 +25520,7 @@ static SDValue LowerLoad(SDValue Op, const X86Subtarget &Subtarget,
"Expected AVX512F without AVX512DQI");
SDValue NewLd = DAG.getLoad(MVT::i8, dl, Ld->getChain(), Ld->getBasePtr(),
- Ld->getPointerInfo(), Ld->getOriginalAlign(),
+ Ld->getPointerInfo(), Ld->getBaseAlign(),
Ld->getMemOperand()->getFlags());
// Replace chain users with the new chain.
@@ -34740,7 +34738,7 @@ void X86TargetLowering::ReplaceNodeResults(SDNode *N,
if (Subtarget.hasSSE2()) {
MVT LdVT = Subtarget.is64Bit() && VT.isInteger() ? MVT::i64 : MVT::f64;
SDValue Res = DAG.getLoad(LdVT, dl, Ld->getChain(), Ld->getBasePtr(),
- Ld->getPointerInfo(), Ld->getOriginalAlign(),
+ Ld->getPointerInfo(), Ld->getBaseAlign(),
Ld->getMemOperand()->getFlags());
SDValue Chain = Res.getValue(1);
MVT VecVT = MVT::getVectorVT(LdVT, 2);
@@ -39065,7 +39063,7 @@ static SDValue narrowLoadToVZLoad(LoadSDNode *LN, MVT MemVT, MVT VT,
SDVTList Tys = DAG.getVTList(VT, MVT::Other);
SDValue Ops[] = {LN->getChain(), LN->getBasePtr()};
return DAG.getMemIntrinsicNode(X86ISD::VZEXT_LOAD, SDLoc(LN), Tys, Ops, MemVT,
- LN->getPointerInfo(), LN->getOriginalAlign(),
+ LN->getPointerInfo(), LN->getBaseAlign(),
LN->getMemOperand()->getFlags());
}
@@ -42178,7 +42176,7 @@ static SDValue combineTargetShuffle(SDValue N, const SDLoc &DL,
SDValue Ops[] = { LN->getChain(), LN->getBasePtr() };
SDValue BcastLd = DAG.getMemIntrinsicNode(
X86ISD::VBROADCAST_LOAD, DL, Tys, Ops, MVT::i16,
- LN->getPointerInfo(), LN->getOriginalAlign(),
+ LN->getPointerInfo(), LN->getBaseAlign(),
LN->getMemOperand()->getFlags());
DCI.CombineTo(N.getNode(), BcastLd);
DAG.ReplaceAllUsesOfValueWith(SDValue(LN, 1), BcastLd.getValue(1));
@@ -42223,8 +42221,7 @@ static SDValue combineTargetShuffle(SDValue N, const SDLoc &DL,
SDValue Ops[] = { LN->getChain(), Ptr };
SDValue BcastLd = DAG.getMemIntrinsicNode(
X86ISD::VBROADCAST_LOAD, DL, Tys, Ops, MVT::i16,
- LN->getPointerInfo().getWithOffset(Offset),
- LN->getOriginalAlign(),
+ LN->getPointerInfo().getWithOffset(Offset), LN->getBaseAlign(),
LN->getMemOperand()->getFlags());
DCI.CombineTo(N.getNode(), BcastLd);
DAG.ReplaceAllUsesOfValueWith(SDValue(LN, 1), BcastLd.getValue(1));
@@ -42259,7 +42256,7 @@ static SDValue combineTargetShuffle(SDValue N, const SDLoc &DL,
SDValue Ops[] = {LN->getChain(), LN->getBasePtr()};
SDValue BcastLd = DAG.getMemIntrinsicNode(
X86ISD::VBROADCAST_LOAD, DL, Tys, Ops, SrcVT.getScalarType(),
- LN->getPointerInfo(), LN->getOriginalAlign(),
+ LN->getPointerInfo(), LN->getBaseAlign(),
LN->getMemOperand()->getFlags());
DCI.CombineTo(N.getNode(), BcastLd);
DAG.ReplaceAllUsesOfValueWith(SDValue(LN, 1), BcastLd.getValue(1));
@@ -46373,11 +46370,10 @@ static SDValue combineExtractWithShuffle(SDNode *N, SelectionDAG &DAG,
unsigned SrcBCWidth = SrcBC.getScalarValueSizeInBits();
if (MemIntr->getMemoryVT().getSizeInBits() == SrcBCWidth &&
VT.getSizeInBits() == SrcBCWidth && SrcEltBits == SrcBCWidth) {
- SDValue Load = DAG.getLoad(VT, dl, MemIntr->getChain(),
- MemIntr->getBasePtr(),
- MemIntr->getPointerInfo(),
- MemIntr->getOriginalAlign(),
- MemIntr->getMemOperand()->getFlags());
+ SDValue Load =
+ DAG.getLoad(VT, dl, MemIntr->getChain(), MemIntr->getBasePtr(),
+ MemIntr->getPointerInfo(), MemIntr->getBaseAlign(),
+ MemIntr->getMemOperand()->getFlags());
DAG.ReplaceAllUsesOfValueWith(SDValue(MemIntr, 1), Load.getValue(1));
return Load;
}
@@ -52951,12 +52947,11 @@ static SDValue combineLoad(SDNode *N, SelectionDAG &DAG,
NumElems / 2);
SDValue Load1 =
DAG.getLoad(HalfVT, dl, Ld->getChain(), Ptr1, Ld->getPointerInfo(),
- Ld->getOriginalAlign(),
- Ld->getMemOperand()->getFlags());
- SDValue Load2 = DAG.getLoad(HalfVT, dl, Ld->getChain(), Ptr2,
- Ld->getPointerInfo().getWithOffset(HalfOffset),
- Ld->getOriginalAlign(),
- Ld->getMemOperand()->getFlags());
+ Ld->getBaseAlign(), Ld->getMemOperand()->getFlags());
+ SDValue Load2 =
+ DAG.getLoad(HalfVT, dl, Ld->getChain(), Ptr2,
+ Ld->getPointerInfo().getWithOffset(HalfOffset),
+ Ld->getBaseAlign(), Ld->getMemOperand()->getFlags());
SDValue TF = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
Load1.getValue(1), Load2.getValue(1));
@@ -52972,8 +52967,7 @@ static SDValue combineLoad(SDNode *N, SelectionDAG &DAG,
EVT IntVT = EVT::getIntegerVT(*DAG.getContext(), NumElts);
if (TLI.isTypeLegal(IntVT)) {
SDValue IntLoad = DAG.getLoad(IntVT, dl, Ld->getChain(), Ld->getBasePtr(),
- Ld->getPointerInfo(),
- Ld->getOriginalAlign(),
+ Ld->getPointerInfo(), Ld->getBaseAlign(),
Ld->getMemOperand()->getFlags());
SDValue BoolVec = DAG.getBitcast(RegVT, IntLoad);
return DCI.CombineTo(N, BoolVec, IntLoad.getValue(1), true);
@@ -53015,7 +53009,7 @@ static SDValue combineLoad(SDNode *N, SelectionDAG &DAG,
SDValue Cast =
DAG.getAddrSpaceCast(dl, PtrVT, Ld->getBasePtr(), AddrSpace, 0);
return DAG.getExtLoad(Ext, dl, RegVT, Ld->getChain(), Cast,
- Ld->getPointerInfo(), MemVT, Ld->getOriginalAlign(),
+ Ld->getPointerInfo(), MemVT, Ld->getBaseAlign(),
Ld->getMemOperand()->getFlags());
}
}
@@ -53081,8 +53075,7 @@ static bool getParamsForOneTrueMaskedElt(MaskedLoadStoreSDNode *MaskedOp,
}
Index = DAG.getIntPtrConstant(TrueMaskElt, SDLoc(MaskedOp));
- Alignment = commonAlignment(MaskedOp->getOriginalAlign(),
- EltVT.getStoreSize());
+ Alignment = commonAlignment(MaskedOp->getBaseAlign(), EltVT.getStoreSize());
return true;
}
@@ -53325,7 +53318,7 @@ static SDValue combineStore(SDNode *N, SelectionDAG &DAG,
StoredVal = DAG.getBitcast(NewVT, StoredVal);
return DAG.getStore(St->getChain(), dl, StoredVal, St->getBasePtr(),
- St->getPointerInfo(), St->getOriginalAlign(),
+ St->getPointerInfo(), St->getBaseAlign(),
St->getMemOperand()->getFlags());
}
@@ -53337,9 +53330,8 @@ static SDValue combineStore(SDNode *N, SelectionDAG &DAG,
SDValue Val = StoredVal.getOperand(0);
// We must store zeros to the unused bits.
Val = DAG.getZeroExtendInReg(Val, dl, MVT::i1);
- return DAG.getStore(St->getChain(), dl, Val,
- St->getBasePtr(), St->getPointerInfo(),
- St->getOriginalAlign(),
+ return DAG.getStore(St->getChain(), dl, Val, St->getBasePtr(),
+ St->getPointerInfo(), St->getBaseAlign(),
St->getMemOperand()->getFlags());
}
@@ -53352,7 +53344,7 @@ static SDValue combineStore(SDNode *N, SelectionDAG &DAG,
Ops[0] = StoredVal;
StoredVal = DAG.getNode(ISD::CONCAT_VECTORS, dl, MVT::v8i1, Ops);
return DAG.getStore(St->getChain(), dl, StoredVal, St->getBasePtr(),
- St->getPointerInfo(), St->getOriginalAlign(),
+ St->getPointerInfo(), St->getBaseAlign(),
St->getMemOperand()->getFlags());
}
@@ -53374,19 +53366,16 @@ static SDValue combineStore(SDNode *N, SelectionDAG &DAG,
SDValue Ch0 =
DAG.getStore(St->getChain(), dl, Lo, Ptr0, St->getPointerInfo(),
- St->getOriginalAlign(),
- St->getMemOperand()->getFlags());
- SDValue Ch1 =
- DAG.getStore(St->getChain(), dl, Hi, Ptr1,
- St->getPointerInfo().getWithOffset(4),
- St->getOriginalAlign(),
- St->getMemOperand()->getFlags());
+ St->getBaseAlign(), St->getMemOperand()->getFlags());
+ SDValue Ch1 = DAG.getStore(
+ St->getChain(), dl, Hi, Ptr1, St->getPointerInfo().getWithOffset(4),
+ St->getBaseAlign(), St->getMemOperand()->getFlags());
return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Ch0, Ch1);
}
StoredVal = combinevXi1ConstantToInteger(StoredVal, DAG);
return DAG.getStore(St->getChain(), dl, StoredVal, St->getBasePtr(),
- St->getPointerInfo(), St->getOriginalAlign(),
+ St->getPointerInfo(), St->getBaseAlign(),
St->getMemOperand()->getFlags());
}
@@ -53408,7 +53397,7 @@ static SDValue combineStore(SDNode *N, SelectionDAG &DAG,
SignOp, dl, IntVT, DAG.getBitcast(IntVT, StoredVal.getOperand(0)),
DAG.getConstant(SignMask, dl, IntVT));
return DAG.getStore(St->getChain(), dl, LogicOp, St->getBasePtr(),
- St->getPointerInfo(), St->getOriginalAlign(),
+ St->getPointerInfo(), St->getBaseAlign(),
St->getMemOperand()->getFlags());
}
}
@@ -53533,8 +53522,7 @@ static SDValue combineStore(SDNode *N, SelectionDAG &DAG,
DAG.getAddrSpaceCast(dl, PtrVT, St->getBasePtr(), AddrSpace, 0);
return DAG.getTruncStore(
St->getChain(), dl, StoredVal, Cast, St->getPointerInfo(), StVT,
- St->getOriginalAlign(), St->getMemOperand()->getFlags(),
- St->getAAInfo());
+ St->getBaseAlign(), St->getMemOperand()->getFlags(), St->getAAInfo());
}
}
@@ -53633,7 +53621,7 @@ static SDValue combineStore(SDNode *N, SelectionDAG &DAG,
SDValue NewExtract = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64,
BitCast, OldExtract.getOperand(1));
return DAG.getStore(St->getChain(), dl, NewExtract, St->getBasePtr(),
- St->getPointerInfo(), St->getOriginalAlign(),
+ St->getPointerInfo(), St->getBaseAlign(),
St->getMemOperand()->getFlags());
}
@@ -57142,7 +57130,7 @@ static SDValue combineSIntToFP(SDNode *N, SelectionDAG &DAG,
std::pair<SDValue, SDValue> Tmp =
Subtarget.getTargetLowering()->BuildFILD(
VT, InVT, SDLoc(N), Ld->getChain(), Ld->getBasePtr(),
- Ld->getPointerInfo(), Ld->getOriginalAlign(), DAG);
+ Ld->getPointerInfo(), Ld->getBaseAlign(), DAG);
DAG.ReplaceAllUsesOfValueWith(Op0.getValue(1), Tmp.second);
return Tmp.first;
}
@@ -59983,7 +59971,7 @@ static SDValue combineEXTEND_VECTOR_INREG(SDNode *N, SelectionDAG &DAG,
if (TLI.isLoadExtLegal(Ext, VT, MemVT)) {
SDValue Load = DAG.getExtLoad(
Ext, DL, VT, Ld->getChain(), Ld->getBasePtr(), Ld->getPointerInfo(),
- MemVT, Ld->getOriginalAlign(), Ld->getMemOperand()->getFlags());
+ MemVT, Ld->getBaseAlign(), Ld->getMemOperand()->getFlags());
DAG.ReplaceAllUsesOfValueWith(SDValue(Ld, 1), Load.getValue(1));
return Load;
}
@@ -60315,11 +60303,10 @@ static SDValue combineMOVDQ2Q(SDNode *N, SelectionDAG &DAG) {
LoadSDNode *LN = cast<LoadSDNode>(Src.getNode());
if (LN->isSimple()) {
- SDValue NewLd = DAG.getLoad(MVT::x86mmx, SDLoc(N), LN->getChain(),
- LN->getBasePtr(),
- LN->getPointerInfo(),
- LN->getOriginalAlign(),
- LN->getMemOperand()->getFlags());
+ SDValue NewLd =
+ DAG.getLoad(MVT::x86mmx, SDLoc(N), LN->getChain(), LN->getBasePtr(),
+ LN->getPointerInfo(), LN->getBaseAlign(),
+ LN->getMemOperand()->getFlags());
DAG.ReplaceAllUsesOfValueWith(SDValue(LN, 1), NewLd.getValue(1));
return NewLd;
}
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