[llvm] ea4bf34 - [RISCV] Add Zilsd to RISCVMergeBaseOffset. (#140157)

[via llvm-commits]

Author: Craig Topper
Date: 2025-05-16T09:37:34-07:00
New Revision: ea4bf3456f775360cbf5de40edb2899a19b33456

URL: https://github.com/llvm/llvm-project/commit/ea4bf3456f775360cbf5de40edb2899a19b33456
DIFF: https://github.com/llvm/llvm-project/commit/ea4bf3456f775360cbf5de40edb2899a19b33456.diff

LOG: [RISCV] Add Zilsd to RISCVMergeBaseOffset. (#140157)

I only tested a simple case for folding the addi from medany codemodel.
I assume everything else should just work.

Added: 
    llvm/test/CodeGen/RISCV/fold-addi-loadstore-zilsd.ll

Modified: 
    llvm/lib/Target/RISCV/RISCVMergeBaseOffset.cpp

Removed: 
    


################################################################################
diff  --git a/llvm/lib/Target/RISCV/RISCVMergeBaseOffset.cpp b/llvm/lib/Target/RISCV/RISCVMergeBaseOffset.cpp
index eb3d43c9af7c2..60ebd0fdff2a8 100644
--- a/llvm/lib/Target/RISCV/RISCVMergeBaseOffset.cpp
+++ b/llvm/lib/Target/RISCV/RISCVMergeBaseOffset.cpp
@@ -409,6 +409,7 @@ bool RISCVMergeBaseOffsetOpt::foldIntoMemoryOps(MachineInstr &Hi,
     case RISCV::LHU:
     case RISCV::LWU:
     case RISCV::LD:
+    case RISCV::LD_RV32:
     case RISCV::FLH:
     case RISCV::FLW:
     case RISCV::FLD:
@@ -418,6 +419,7 @@ bool RISCVMergeBaseOffsetOpt::foldIntoMemoryOps(MachineInstr &Hi,
     case RISCV::SW:
     case RISCV::SW_INX:
     case RISCV::SD:
+    case RISCV::SD_RV32:
     case RISCV::FSH:
     case RISCV::FSW:
     case RISCV::FSD: {

diff  --git a/llvm/test/CodeGen/RISCV/fold-addi-loadstore-zilsd.ll b/llvm/test/CodeGen/RISCV/fold-addi-loadstore-zilsd.ll
new file mode 100644
index 0000000000000..e34c5272ebaeb
--- /dev/null
+++ b/llvm/test/CodeGen/RISCV/fold-addi-loadstore-zilsd.ll
@@ -0,0 +1,30 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -mtriple=riscv32 -mattr=+zdinx,+zilsd -verify-machineinstrs \
+; RUN:   -code-model=medium < %s | FileCheck %s
+
+ at g_0 = global double 0.0
+
+define double @load_g_0() nounwind {
+; CHECK-LABEL: load_g_0:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:  .Lpcrel_hi0:
+; CHECK-NEXT:    auipc a0, %pcrel_hi(g_0)
+; CHECK-NEXT:    ld a0, %pcrel_lo(.Lpcrel_hi0)(a0)
+; CHECK-NEXT:    ret
+entry:
+  %0 = load double, ptr @g_0
+  ret double %0
+}
+
+define void @store_g_0() nounwind {
+; CHECK-LABEL: store_g_0:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:  .Lpcrel_hi1:
+; CHECK-NEXT:    auipc a0, %pcrel_hi(g_0)
+; CHECK-NEXT:    fcvt.d.w a2, zero
+; CHECK-NEXT:    sd a2, %pcrel_lo(.Lpcrel_hi1)(a0)
+; CHECK-NEXT:    ret
+entry:
+  store double 0.0, ptr @g_0
+  ret void
+}