[llvm] 7f4a910 - [RISCV] Add Zilsd/Zclsd support to RISCVMakeCompressible. (#140136)
via llvm-commits
llvm-commits at lists.llvm.org
Fri May 16 09:36:43 PDT 2025
Author: Craig Topper
Date: 2025-05-16T09:36:39-07:00
New Revision: 7f4a9105df26a1c481d6b6d390a9d24e8ea987d1
URL: https://github.com/llvm/llvm-project/commit/7f4a9105df26a1c481d6b6d390a9d24e8ea987d1
DIFF: https://github.com/llvm/llvm-project/commit/7f4a9105df26a1c481d6b6d390a9d24e8ea987d1.diff
LOG: [RISCV] Add Zilsd/Zclsd support to RISCVMakeCompressible. (#140136)
Added:
llvm/test/CodeGen/RISCV/make-compressible-zilsd.mir
Modified:
llvm/lib/Target/RISCV/RISCVMakeCompressible.cpp
Removed:
################################################################################
diff --git a/llvm/lib/Target/RISCV/RISCVMakeCompressible.cpp b/llvm/lib/Target/RISCV/RISCVMakeCompressible.cpp
index 5453753fa4579..1e2bdb10aa810 100644
--- a/llvm/lib/Target/RISCV/RISCVMakeCompressible.cpp
+++ b/llvm/lib/Target/RISCV/RISCVMakeCompressible.cpp
@@ -116,7 +116,9 @@ static unsigned log2LdstWidth(unsigned Opcode) {
case RISCV::FSW:
return 2;
case RISCV::LD:
+ case RISCV::LD_RV32:
case RISCV::SD:
+ case RISCV::SD_RV32:
case RISCV::FLD:
case RISCV::FSD:
return 3;
@@ -144,7 +146,9 @@ static unsigned offsetMask(unsigned Opcode) {
case RISCV::FLW:
case RISCV::FSW:
case RISCV::LD:
+ case RISCV::LD_RV32:
case RISCV::SD:
+ case RISCV::SD_RV32:
case RISCV::FLD:
case RISCV::FSD:
return maskTrailingOnes<unsigned>(5U);
@@ -184,7 +188,8 @@ static bool isCompressedReg(Register Reg) {
RISCV::GPRF16CRegClass.contains(Reg) ||
RISCV::GPRF32CRegClass.contains(Reg) ||
RISCV::FPR32CRegClass.contains(Reg) ||
- RISCV::FPR64CRegClass.contains(Reg);
+ RISCV::FPR64CRegClass.contains(Reg) ||
+ RISCV::GPRPairCRegClass.contains(Reg);
}
// Return true if MI is a load for which there exists a compressed version.
@@ -203,6 +208,8 @@ static bool isCompressibleLoad(const MachineInstr &MI) {
case RISCV::LW_INX:
case RISCV::LD:
return STI.hasStdExtCOrZca();
+ case RISCV::LD_RV32:
+ return STI.hasStdExtZclsd();
case RISCV::FLW:
return !STI.is64Bit() && STI.hasStdExtCOrZcfOrZce();
case RISCV::FLD:
@@ -225,6 +232,8 @@ static bool isCompressibleStore(const MachineInstr &MI) {
case RISCV::SW_INX:
case RISCV::SD:
return STI.hasStdExtCOrZca();
+ case RISCV::SD_RV32:
+ return STI.hasStdExtZclsd();
case RISCV::FSW:
return !STI.is64Bit() && STI.hasStdExtCOrZcfOrZce();
case RISCV::FSD:
@@ -342,8 +351,10 @@ static Register analyzeCompressibleUses(MachineInstr &FirstMI,
RCToScavenge = &RISCV::FPR32CRegClass;
else if (RISCV::FPR64RegClass.contains(RegImm.Reg))
RCToScavenge = &RISCV::FPR64CRegClass;
+ else if (RISCV::GPRPairRegClass.contains(RegImm.Reg))
+ RCToScavenge = &RISCV::GPRPairCRegClass;
else
- return RISCV::NoRegister;
+ return Register();
RegScavenger RS;
RS.enterBasicBlockEnd(MBB);
@@ -400,6 +411,7 @@ bool RISCVMakeCompressibleOpt::runOnMachineFunction(MachineFunction &Fn) {
const RISCVSubtarget &STI = Fn.getSubtarget<RISCVSubtarget>();
const RISCVInstrInfo &TII = *STI.getInstrInfo();
+ const RISCVRegisterInfo &TRI = *STI.getRegisterInfo();
// This optimization only makes sense if compressed instructions are emitted.
if (!STI.hasStdExtCOrZca())
@@ -438,7 +450,20 @@ bool RISCVMakeCompressibleOpt::runOnMachineFunction(MachineFunction &Fn) {
BuildMI(MBB, MI, MI.getDebugLoc(), TII.get(RISCV::PseudoMV_FPR32INX),
NewReg)
.addReg(RegImm.Reg);
+ } else if (RISCV::GPRPairRegClass.contains(RegImm.Reg)) {
+ assert(RegImm.Imm == 0);
+ BuildMI(MBB, MI, MI.getDebugLoc(), TII.get(RISCV::ADDI),
+ TRI.getSubReg(NewReg, RISCV::sub_gpr_even))
+ .addReg(TRI.getSubReg(RegImm.Reg, RISCV::sub_gpr_even))
+ .addImm(0);
+ BuildMI(MBB, MI, MI.getDebugLoc(), TII.get(RISCV::ADDI),
+ TRI.getSubReg(NewReg, RISCV::sub_gpr_odd))
+ .addReg(TRI.getSubReg(RegImm.Reg, RISCV::sub_gpr_odd))
+ .addImm(0);
} else {
+ assert((RISCV::FPR32RegClass.contains(RegImm.Reg) ||
+ RISCV::FPR64RegClass.contains(RegImm.Reg)) &&
+ "Expected FP register class");
// If we are looking at replacing an FPR register we don't expect to
// have any offset. The only compressible FP instructions with an offset
// are loads and stores, for which the offset applies to the GPR operand
diff --git a/llvm/test/CodeGen/RISCV/make-compressible-zilsd.mir b/llvm/test/CodeGen/RISCV/make-compressible-zilsd.mir
new file mode 100644
index 0000000000000..c5ac599d8d53f
--- /dev/null
+++ b/llvm/test/CodeGen/RISCV/make-compressible-zilsd.mir
@@ -0,0 +1,299 @@
+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 5
+# RUN: llc -o - %s -mtriple=riscv32 -mattr=+zilsd,+zclsd,+zdinx -simplify-mir \
+# RUN: -run-pass=riscv-make-compressible | FileCheck --check-prefixes=RV32 %s
+--- |
+ define void @store_common_value_double(ptr %a, ptr %b, ptr %c, i32 %d, double %e, double %f) #0 {
+ entry:
+ store double %f, ptr %a, align 8
+ store double %f, ptr %b, align 8
+ store double %f, ptr %c, align 8
+ ret void
+ }
+
+ define void @store_common_ptr_double(double %a, double %b, double %d, ptr %p) #0 {
+ entry:
+ store volatile double %a, ptr %p, align 8
+ store volatile double %b, ptr %p, align 8
+ store volatile double %b, ptr %p, align 8
+ ret void
+ }
+
+ define void @load_common_ptr_double(i32 %a, i32 %b, i32 %c, i32 %d, i32 %e, i32 %f, ptr %g) #0 {
+ entry:
+ %0 = load double, ptr %g, align 8
+ %arrayidx1 = getelementptr inbounds { double, double, i32 }, ptr %g, i32 0, i32 1
+ %1 = load double, ptr %arrayidx1, align 8
+ %arrayidx2 = getelementptr inbounds { double, double, i32 }, ptr %g, i32 0, i32 2
+ %2 = load i32, ptr %arrayidx2, align 8
+ tail call void @load_common_ptr_double_1(double %0, double %1, i32 %2)
+ ret void
+ }
+
+ declare void @load_common_ptr_double_1(double, double, double) #0
+
+ define void @store_large_offset_double(ptr %p, i32 %dummy, double %a, double %b, double %c) #0 {
+ entry:
+ %0 = getelementptr inbounds double, ptr %p, i32 100
+ store volatile double %a, ptr %0, align 8
+ %1 = getelementptr inbounds double, ptr %p, i32 101
+ store volatile double %b, ptr %1, align 8
+ %2 = getelementptr inbounds double, ptr %p, i32 102
+ store volatile double %b, ptr %2, align 8
+ ret void
+ }
+
+ define void @load_large_offset_double(i32 %a, i32 %b, i32 %c, i32 %d, ptr %p) #0 {
+ entry:
+ %arrayidx = getelementptr inbounds { [102 x double], i32 }, ptr %p, i32 0, i32 0, i32 100
+ %0 = load double, ptr %arrayidx, align 8
+ %arrayidx1 = getelementptr inbounds { [102 x double], i32 }, ptr %p, i32 0, i32 0, i32 101
+ %1 = load double, ptr %arrayidx1, align 8
+ %arrayidx2 = getelementptr inbounds { [102 x double], i32 }, ptr %p, i32 0, i32 1
+ %2 = load i32, ptr %arrayidx2, align 8
+ tail call void @load_large_offset_double_1(double %0, double %1, i32 %2)
+ ret void
+ }
+
+ declare void @load_large_offset_double_1(double, double) #0
+
+ define void @store_common_value_double_no_opt(ptr %a, i32 %b, double %c, double %d, double %e) #0 {
+ entry:
+ store double %e, ptr %a, align 8
+ ret void
+ }
+
+ define void @store_common_ptr_double_no_opt(double %a, i32 %b, i32 %c, i32 %d, i32 %e, ptr %p) #0 {
+ entry:
+ store volatile double %a, ptr %p, align 8
+ ret void
+ }
+
+ define double @load_common_ptr_double_no_opt(i32 %a, i32 %b, i32 %c, i32 %d, i32 %e, i32 %f, ptr %g) #0 {
+ entry:
+ %0 = load double, ptr %g, align 8
+ ret double %0
+ }
+
+ define void @store_large_offset_double_no_opt(ptr %p, double %a, double %b) #0 {
+ entry:
+ %0 = getelementptr inbounds double, ptr %p, i32 100
+ store volatile double %a, ptr %0, align 8
+ %1 = getelementptr inbounds double, ptr %p, i32 101
+ store volatile double %b, ptr %1, align 8
+ ret void
+ }
+
+ define { double, double } @load_large_offset_double_no_opt(ptr %p) #0 {
+ entry:
+ %arrayidx = getelementptr inbounds double, ptr %p, i32 100
+ %0 = load double, ptr %arrayidx, align 8
+ %arrayidx1 = getelementptr inbounds double, ptr %p, i32 101
+ %1 = load double, ptr %arrayidx1, align 8
+ %2 = insertvalue { double, double } undef, double %0, 0
+ %3 = insertvalue { double, double } %2, double %1, 1
+ ret { double, double } %3
+ }
+
+ attributes #0 = { minsize "target-features"="+zilsd,+zdinx" }
+...
+---
+name: store_common_value_double
+tracksRegLiveness: true
+body: |
+ bb.0.entry:
+ liveins: $x10, $x11, $x12, $x16, $x17
+
+ ; RV32-LABEL: name: store_common_value_double
+ ; RV32: liveins: $x10, $x11, $x12, $x16, $x17
+ ; RV32-NEXT: {{ $}}
+ ; RV32-NEXT: $x14 = ADDI $x16, 0
+ ; RV32-NEXT: $x15 = ADDI $x17, 0
+ ; RV32-NEXT: SD_RV32 $x14_x15, killed renamable $x10, 0 :: (store (s64) into %ir.a)
+ ; RV32-NEXT: SD_RV32 $x14_x15, killed renamable $x11, 0 :: (store (s64) into %ir.b)
+ ; RV32-NEXT: SD_RV32 killed $x14_x15, killed renamable $x12, 0 :: (store (s64) into %ir.c)
+ ; RV32-NEXT: PseudoRET
+ SD_RV32 renamable $x16_x17, killed renamable $x10, 0 :: (store (s64) into %ir.a)
+ SD_RV32 renamable $x16_x17, killed renamable $x11, 0 :: (store (s64) into %ir.b)
+ SD_RV32 killed renamable $x16_x17, killed renamable $x12, 0 :: (store (s64) into %ir.c)
+ PseudoRET
+
+...
+---
+name: store_common_ptr_double
+tracksRegLiveness: true
+body: |
+ bb.0.entry:
+ liveins: $x10, $x11, $x12, $x13, $x14, $x15, $x16
+
+ ; RV32-LABEL: name: store_common_ptr_double
+ ; RV32: liveins: $x10, $x11, $x12, $x13, $x14, $x15, $x16
+ ; RV32-NEXT: {{ $}}
+ ; RV32-NEXT: $x14 = ADDI $x16, 0
+ ; RV32-NEXT: SD_RV32 killed renamable $x10_x11, $x14, 0 :: (volatile store (s64) into %ir.p)
+ ; RV32-NEXT: SD_RV32 renamable $x12_x13, $x14, 0 :: (volatile store (s64) into %ir.p)
+ ; RV32-NEXT: SD_RV32 killed renamable $x12_x13, killed $x14, 0 :: (volatile store (s64) into %ir.p)
+ ; RV32-NEXT: PseudoRET
+ SD_RV32 killed renamable $x10_x11, renamable $x16, 0 :: (volatile store (s64) into %ir.p)
+ SD_RV32 renamable $x12_x13, renamable $x16, 0 :: (volatile store (s64) into %ir.p)
+ SD_RV32 killed renamable $x12_x13, killed renamable $x16, 0 :: (volatile store (s64) into %ir.p)
+ PseudoRET
+
+...
+---
+name: load_common_ptr_double
+tracksRegLiveness: true
+body: |
+ bb.0.entry:
+ liveins: $x16
+
+ ; RV32-LABEL: name: load_common_ptr_double
+ ; RV32: liveins: $x16
+ ; RV32-NEXT: {{ $}}
+ ; RV32-NEXT: $x15 = ADDI $x16, 0
+ ; RV32-NEXT: renamable $x10_x11 = LD_RV32 $x15, 0 :: (load (s64) from %ir.g)
+ ; RV32-NEXT: renamable $x12_x13 = LD_RV32 $x15, 8 :: (load (s64) from %ir.arrayidx1)
+ ; RV32-NEXT: renamable $x14 = LW killed $x15, 16 :: (load (s32) from %ir.arrayidx2, align 8)
+ ; RV32-NEXT: PseudoTAIL target-flags(riscv-call) @load_common_ptr_double_1, csr_ilp32_lp64, implicit $x2, implicit $x10, implicit $x11, implicit $x12, implicit $x13, implicit $x14
+ renamable $x10_x11 = LD_RV32 renamable $x16, 0 :: (load (s64) from %ir.g)
+ renamable $x12_x13 = LD_RV32 renamable $x16, 8 :: (load (s64) from %ir.arrayidx1)
+ renamable $x14 = LW killed renamable $x16, 16 :: (load (s32) from %ir.arrayidx2, align 8)
+ PseudoTAIL target-flags(riscv-call) @load_common_ptr_double_1, csr_ilp32_lp64, implicit $x2, implicit $x10, implicit $x11, implicit $x12, implicit $x13, implicit $x14
+
+...
+---
+name: store_large_offset_double
+tracksRegLiveness: true
+body: |
+ bb.0.entry:
+ liveins: $x10, $x12, $x13, $x14, $x15
+
+ ; RV32-LABEL: name: store_large_offset_double
+ ; RV32: liveins: $x10, $x12, $x13, $x14, $x15
+ ; RV32-NEXT: {{ $}}
+ ; RV32-NEXT: $x11 = ADDI $x10, 768
+ ; RV32-NEXT: SD_RV32 killed renamable $x12_x13, $x11, 32 :: (volatile store (s64) into %ir.0)
+ ; RV32-NEXT: SD_RV32 renamable $x14_x15, $x11, 40 :: (volatile store (s64) into %ir.1)
+ ; RV32-NEXT: SD_RV32 killed renamable $x14_x15, killed $x11, 48 :: (volatile store (s64) into %ir.2)
+ ; RV32-NEXT: PseudoRET
+ SD_RV32 killed renamable $x12_x13, renamable $x10, 800 :: (volatile store (s64) into %ir.0)
+ SD_RV32 renamable $x14_x15, renamable $x10, 808 :: (volatile store (s64) into %ir.1)
+ SD_RV32 killed renamable $x14_x15, killed renamable $x10, 816 :: (volatile store (s64) into %ir.2)
+ PseudoRET
+
+...
+---
+name: load_large_offset_double
+tracksRegLiveness: true
+body: |
+ bb.0.entry:
+ liveins: $x14
+
+ ; RV32-LABEL: name: load_large_offset_double
+ ; RV32: liveins: $x14
+ ; RV32-NEXT: {{ $}}
+ ; RV32-NEXT: $x15 = ADDI $x14, 768
+ ; RV32-NEXT: renamable $x10_x11 = LD_RV32 $x15, 32 :: (load (s64) from %ir.arrayidx)
+ ; RV32-NEXT: renamable $x12_x13 = LD_RV32 $x15, 40 :: (load (s64) from %ir.arrayidx1)
+ ; RV32-NEXT: renamable $x14 = LW killed $x15, 48 :: (load (s32) from %ir.arrayidx2, align 8)
+ ; RV32-NEXT: PseudoTAIL target-flags(riscv-call) @load_large_offset_double_1, csr_ilp32_lp64, implicit $x2, implicit $x10, implicit $x11, implicit $x12, implicit $x13, implicit $x14
+ renamable $x10_x11 = LD_RV32 renamable $x14, 800 :: (load (s64) from %ir.arrayidx)
+ renamable $x12_x13 = LD_RV32 renamable $x14, 808 :: (load (s64) from %ir.arrayidx1)
+ renamable $x14 = LW killed renamable $x14, 816 :: (load (s32) from %ir.arrayidx2, align 8)
+ PseudoTAIL target-flags(riscv-call) @load_large_offset_double_1, csr_ilp32_lp64, implicit $x2, implicit $x10, implicit $x11, implicit $x12, implicit $x13, implicit $x14
+...
+---
+name: store_common_value_double_no_opt
+tracksRegLiveness: true
+body: |
+ bb.0.entry:
+ liveins: $x10, $x16, $x17
+
+ ; RV32-LABEL: name: store_common_value_double_no_opt
+ ; RV32: liveins: $x10, $x16, $x17
+ ; RV32-NEXT: {{ $}}
+ ; RV32-NEXT: SD_RV32 killed renamable $x16_x17, killed renamable $x10, 0 :: (store (s64) into %ir.a)
+ ; RV32-NEXT: PseudoRET
+ SD_RV32 killed renamable $x16_x17, killed renamable $x10, 0 :: (store (s64) into %ir.a)
+ PseudoRET
+
+...
+---
+name: store_common_ptr_double_no_opt
+tracksRegLiveness: true
+body: |
+ bb.0.entry:
+ liveins: $x10, $x11, $x16
+
+ ; RV32-LABEL: name: store_common_ptr_double_no_opt
+ ; RV32: liveins: $x10, $x11, $x16
+ ; RV32-NEXT: {{ $}}
+ ; RV32-NEXT: SD_RV32 killed renamable $x10_x11, killed renamable $x16, 0 :: (volatile store (s64) into %ir.p)
+ ; RV32-NEXT: PseudoRET
+ SD_RV32 killed renamable $x10_x11, killed renamable $x16, 0 :: (volatile store (s64) into %ir.p)
+ PseudoRET
+
+...
+---
+name: load_common_ptr_double_no_opt
+tracksRegLiveness: true
+body: |
+ bb.0.entry:
+ liveins: $x16
+
+ ; RV32-LABEL: name: load_common_ptr_double_no_opt
+ ; RV32: liveins: $x16
+ ; RV32-NEXT: {{ $}}
+ ; RV32-NEXT: renamable $x10_x11 = LD_RV32 killed renamable $x16, 0 :: (load (s64) from %ir.g)
+ ; RV32-NEXT: PseudoRET implicit $x10, implicit $x11
+ renamable $x10_x11 = LD_RV32 killed renamable $x16, 0 :: (load (s64) from %ir.g)
+ PseudoRET implicit $x10, implicit $x11
+
+...
+---
+name: store_large_offset_double_no_opt
+tracksRegLiveness: true
+body: |
+ bb.0.entry:
+ liveins: $x10, $x11, $x12, $x13, $x14
+
+ ; RV32-LABEL: name: store_large_offset_double_no_opt
+ ; RV32: liveins: $x10, $x11, $x12, $x13, $x14
+ ; RV32-NEXT: {{ $}}
+ ; RV32-NEXT: $x15 = ADDI $x14, 0
+ ; RV32-NEXT: $x17 = ADDI $x12, 0
+ ; RV32-NEXT: $x16 = ADDI $x11, 0
+ ; RV32-NEXT: SD_RV32 killed renamable $x16_x17, renamable $x10, 800 :: (volatile store (s64) into %ir.0)
+ ; RV32-NEXT: $x14 = ADDI $x13, 0
+ ; RV32-NEXT: SD_RV32 killed renamable $x14_x15, killed renamable $x10, 808 :: (volatile store (s64) into %ir.1)
+ ; RV32-NEXT: PseudoRET
+ $x15 = ADDI $x14, 0
+ $x17 = ADDI $x12, 0
+ $x16 = ADDI $x11, 0
+ SD_RV32 killed renamable $x16_x17, renamable $x10, 800 :: (volatile store (s64) into %ir.0)
+ $x14 = ADDI $x13, 0
+ SD_RV32 killed renamable $x14_x15, killed renamable $x10, 808 :: (volatile store (s64) into %ir.1)
+ PseudoRET
+
+...
+---
+name: load_large_offset_double_no_opt
+tracksRegLiveness: true
+body: |
+ bb.0.entry:
+ liveins: $x10
+
+ ; RV32-LABEL: name: load_large_offset_double_no_opt
+ ; RV32: liveins: $x10
+ ; RV32-NEXT: {{ $}}
+ ; RV32-NEXT: renamable $x14_x15 = LD_RV32 renamable $x10, 800 :: (load (s64) from %ir.arrayidx)
+ ; RV32-NEXT: renamable $x12_x13 = LD_RV32 killed renamable $x10, 808 :: (load (s64) from %ir.arrayidx1)
+ ; RV32-NEXT: $x10 = ADDI renamable $x14, 0
+ ; RV32-NEXT: $x11 = ADDI killed renamable $x15, 0
+ ; RV32-NEXT: PseudoRET implicit $x10, implicit $x11, implicit $x12, implicit $x13
+ renamable $x14_x15 = LD_RV32 renamable $x10, 800 :: (load (s64) from %ir.arrayidx)
+ renamable $x12_x13 = LD_RV32 killed renamable $x10, 808 :: (load (s64) from %ir.arrayidx1)
+ $x10 = ADDI renamable $x14, 0
+ $x11 = ADDI killed renamable $x15, 0
+ PseudoRET implicit $x10, implicit $x11, implicit $x12, implicit $x13
+
+...
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