[llvm] [RISCV] Split f64 loads/stores for RV32+Zdinx during isel instead of post-RA. (PR #139840)

[Philip Reames via llvm-commits]

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@@ -7748,13 +7776,34 @@ SDValue RISCVTargetLowering::LowerOperation(SDValue Op,
   case ISD::STORE: {
     auto *Store = cast<StoreSDNode>(Op);
     SDValue StoredVal = Store->getValue();
-    EVT VecTy = StoredVal.getValueType();
+    EVT VT = StoredVal.getValueType();
+    if (VT == MVT::f64) {
+      assert(Subtarget.hasStdExtZdinx() && !Subtarget.is64Bit() &&
+             "Unexpected custom legalisation");
+
+      // Replace a double precision store with a SplitF64 and i32 stores.
+      SDValue DL(Op);
+      SDValue BasePtr = Store->getBasePtr();
+      SDValue Chain = Store->getChain();
+      SDValue Split = DAG.getNode(RISCVISD::SplitF64, DL,
+                                  DAG.getVTList(MVT::i32, MVT::i32), StoredVal);
+
+      SDValue Lo = DAG.getStore(
+          Chain, DL, Split.getValue(0), BasePtr, Store->getPointerInfo(),
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preames wrote:

Same problems with size and alignment here.

https://github.com/llvm/llvm-project/pull/139840