[llvm] [RISCV] Split f64 loads/stores for RV32+Zdinx during isel instead of post-RA. (PR #139840)

[Craig Topper via llvm-commits]

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@@ -7705,19 +7710,42 @@ SDValue RISCVTargetLowering::LowerOperation(SDValue Op,
   }
   case ISD::LOAD: {
     auto *Load = cast<LoadSDNode>(Op);
-    EVT VecTy = Load->getMemoryVT();
+    EVT VT = Load->getValueType(0);
+    if (VT == MVT::f64) {
+      assert(Subtarget.hasStdExtZdinx() && !Subtarget.is64Bit() &&
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topperc wrote:

The expansion of f64 load would happen in LegalizeDAG. LegalizeDAG is not allowed to produce illegal types. It will hit an assertion.

https://github.com/llvm/llvm-project/pull/139840