[llvm] [RISCV] Split f64 loads/stores for RV32+Zdinx during isel instead of post-RA. (PR #139840)

[Philip Reames via llvm-commits]

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@@ -7705,19 +7710,42 @@ SDValue RISCVTargetLowering::LowerOperation(SDValue Op,
   }
   case ISD::LOAD: {
     auto *Load = cast<LoadSDNode>(Op);
-    EVT VecTy = Load->getMemoryVT();
+    EVT VT = Load->getValueType(0);
+    if (VT == MVT::f64) {
+      assert(Subtarget.hasStdExtZdinx() && !Subtarget.is64Bit() &&
+             "Unexpected custom legalisation");
+
+      // Replace a double precision load with two i32 loads and a BuildPairF64.
+      SDLoc DL(Op);
+      SDValue BasePtr = Load->getBasePtr();
+      SDValue Chain = Load->getChain();
+
+      SDValue Lo = DAG.getLoad(MVT::i32, DL, Chain, BasePtr,
+                               Load->getPointerInfo(), Load->getOriginalAlign(),
+                               Load->getMemOperand()->getFlags());
+      BasePtr = DAG.getObjectPtrOffset(DL, BasePtr, TypeSize::getFixed(4));
+      SDValue Hi = DAG.getLoad(
+          MVT::i32, DL, Chain, BasePtr, Load->getPointerInfo().getWithOffset(4),
+          Load->getOriginalAlign(), Load->getMemOperand()->getFlags());
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preames wrote:

The original align here is wrong.  Assume original align 8, the second load needs align 4.  

https://github.com/llvm/llvm-project/pull/139840