[llvm] Adding support in llvm-exegesis for Aarch64 for handling FPR64/128, PPR16 and ZPR128 reg class. (PR #127564)

[via llvm-commits]

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@@ -28,13 +28,66 @@ static unsigned getLoadImmediateOpcode(unsigned RegBitWidth) {
 // Generates instruction to load an immediate value into a register.
 static MCInst loadImmediate(MCRegister Reg, unsigned RegBitWidth,
                             const APInt &Value) {
-  if (Value.getBitWidth() > RegBitWidth)
-    llvm_unreachable("Value must fit in the Register");
+  // 0 <= Value.getZExtValue() < 2**16
+  assert(Value.getZExtValue() < (1 << 16) &&
+         "Value must be in the range of the immediate opcode");
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lakshayk-nv wrote:

Yes, `MOVi32imm` and `MOVi64imm` are pseudo-instructions that decompose into the MOV instruction, such as mov w21, #0x0, as seen in disassembly using GPR32/64 for opcodes like `LSRVWr`.
The assertion primarily ensures codebase consistency. In practice, setRegTo is almost always used to set a register to zero.
Since the MOV instruction accepts a 16-bit immediate, the upper bound check is set to 2^16 accordingly. [[Referred ISA doc here]](https://developer.arm.com/documentation/ddi0602/2021-12/Base-Instructions/MOV--wide-immediate---Move--wide-immediate---an-alias-of-MOVZ-?lang=en).

PS: I tried with larger value setting using the pseudo, it works for larger values than 2^16. In my opinion, we can skip the assert. What do you think ?

https://github.com/llvm/llvm-project/pull/127564