[llvm] Adding support in llvm-exegesis for Aarch64 for handling FPR64/128, PPR16 and ZPR128 reg class. (PR #127564)

[via llvm-commits]

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@@ -28,13 +28,51 @@ static unsigned getLoadImmediateOpcode(unsigned RegBitWidth) {
 // Generates instruction to load an immediate value into a register.
 static MCInst loadImmediate(MCRegister Reg, unsigned RegBitWidth,
                             const APInt &Value) {
-  if (Value.getBitWidth() > RegBitWidth)
-    llvm_unreachable("Value must fit in the Register");
+  assert(Value.getBitWidth() <= RegBitWidth && "Value must fit in the Register"); 
   return MCInstBuilder(getLoadImmediateOpcode(RegBitWidth))
       .addReg(Reg)
       .addImm(Value.getZExtValue());
 }
 
+static MCInst loadZPRImmediate(MCRegister Reg, unsigned RegBitWidth,
+                               const APInt &Value) {
+  assert(Value.getBitWidth() <= RegBitWidth && "Value must fit in the PPR Register");
+  // For ZPR, we typically use DUPM instruction to load immediate values
+  return MCInstBuilder(AArch64::DUPM_ZI)
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lakshayk-nv wrote:

ZPR Reg Class seems to require DUPM. 
DUP has only variants for 8 bits to 64 bits (DUPi8, DIPi16, DUPi32, DUPi64) which can't set a vector 
For opcode FADDV_VPZ_D when tried to use base instruction DUPi64, It tries ` $z6 = DUPi64 0` which throws error `$z6 is not a FPR64 register.` .


https://github.com/llvm/llvm-project/pull/127564