[llvm] Adding support in llvm-exegesis for Aarch64 for handling FPR64/128, PPR16 and ZPR128 reg class. (PR #127564)

[via llvm-commits]

================
@@ -28,13 +28,51 @@ static unsigned getLoadImmediateOpcode(unsigned RegBitWidth) {
 // Generates instruction to load an immediate value into a register.
 static MCInst loadImmediate(MCRegister Reg, unsigned RegBitWidth,
                             const APInt &Value) {
-  if (Value.getBitWidth() > RegBitWidth)
-    llvm_unreachable("Value must fit in the Register");
+  assert(Value.getBitWidth() <= RegBitWidth && "Value must fit in the Register"); 
   return MCInstBuilder(getLoadImmediateOpcode(RegBitWidth))
       .addReg(Reg)
       .addImm(Value.getZExtValue());
 }
 
+static MCInst loadZPRImmediate(MCRegister Reg, unsigned RegBitWidth,
+                               const APInt &Value) {
+  assert(Value.getBitWidth() <= RegBitWidth && "Value must fit in the PPR Register");
+  // For ZPR, we typically use DUPM instruction to load immediate values
+  return MCInstBuilder(AArch64::DUPM_ZI)
+      .addReg(Reg)
+      .addImm(Value.getZExtValue());
+}
+
+static MCInst loadPPRImmediate(MCRegister Reg, unsigned RegBitWidth,
+                               const APInt &Value) {
+  assert(Value.getBitWidth() <= RegBitWidth && "Value must fit in the PPR Register"); 
+  // For PPR, we typically use PTRUE instruction to set predicate registers
+  return MCInstBuilder(AArch64::PTRUE_B)
+      .addReg(Reg)
+      .addImm(0xFFFF); // All lanes true for 16 bits
+}
+
+// Generates instruction to load an FP immediate value into a register.
+static unsigned getLoadFPImmediateOpcode(unsigned RegBitWidth) {
+  switch (RegBitWidth) {
+  case 64:
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lakshayk-nv wrote:

Yes, We will be adding support for other smaller reg classes in coming patches.
We tried moving value (FP64) in lower bit register classes (FPR32/16/8. But they requires different base base instructions;  

I checked it, by moving FPR8 RegClass with FMOVDi; (FPR8 required by SQABSv1i8 opcode). Similarly for FPR16 and FPR32.
It throws error `Bad machine code: Illegal physical register for instruction`
```
bb.0:
  $b8 = FMOVDi 0
  $b8 = SQABSv1i8 $b8
  $b8 = SQABSv1i8 $b8
  $b8 = SQABSv1i8 $b8
  $b8 = SQABSv1i8 $b8
  RET undef $lr

# End machine code for function foo.

*** Bad machine code: Illegal physical register for instruction ***
- function:    foo
- basic block: %bb.0  (0xaaaab3f75530)
- instruction: $b8 = FMOVDi 0
- operand 0:   $b8
$b8 is not a FPR64 register.
LLVM ERROR: Found 1 machine code errors.```

In next patch we will push immediate using required base instruction for other smaller reg classes.

https://github.com/llvm/llvm-project/pull/127564