[llvm] [AArch64] Combine and and lsl into ubfiz (PR #118974)

[David Sherwood via llvm-commits]

================
@@ -26057,6 +26059,38 @@ performScalarToVectorCombine(SDNode *N, TargetLowering::DAGCombinerInfo &DCI,
   return NVCAST;
 }
 
+static SDValue performSHLCombine(SDNode *N, SelectionDAG &DAG) {
+  SDValue Op0 = N->getOperand(0);
+  SDValue Op1 = N->getOperand(1);
+  EVT VT = N->getValueType(0);
+  if (VT != MVT::i32 && VT != MVT::i64)
+    return SDValue();
+
+  // If the operand is a bitwise AND with a constant RHS, and the shift is the
+  // only use, we can pull it out of the shift.
+  //
+  // (shl (and X, C1), C2) -> (and (shl X, C2), (shl C1, C2))
+  if (!Op0.hasOneUse() || Op0.getOpcode() != ISD::AND)
+    return SDValue();
+
+  ConstantSDNode *C1 = dyn_cast<ConstantSDNode>(Op0.getOperand(1));
+  ConstantSDNode *C2 = dyn_cast<ConstantSDNode>(Op1);
+  if (!C1 || !C2)
+    return SDValue();
+
+  // Might be folded into shifted op, do not lower.
+  unsigned UseOpc = N->use_begin()->getOpcode();
----------------
david-arm wrote:

I'm not sure if this is safe. What if `N` has no uses? You might need to do something like:

```
  if (N->hasOneUse() {
    unsigned UseOpc = N->use_begin()->getOpcode();
...
  }
```

https://github.com/llvm/llvm-project/pull/118974