[llvm] [AArch64] Combine and and lsl into ubfiz (PR #118974)

[David Sherwood via llvm-commits]

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@@ -26057,6 +26059,38 @@ performScalarToVectorCombine(SDNode *N, TargetLowering::DAGCombinerInfo &DCI,
   return NVCAST;
 }
 
+static SDValue performSHLCombine(SDNode *N, SelectionDAG &DAG) {
+  SDValue Op0 = N->getOperand(0);
+  SDValue Op1 = N->getOperand(1);
+  EVT VT = N->getValueType(0);
+  if (VT != MVT::i32 && VT != MVT::i64)
+    return SDValue();
+
+  // If the operand is a bitwise AND with a constant RHS, and the shift is the
+  // only use, we can pull it out of the shift.
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david-arm wrote:

nit: // and the shift has a constant RHS and is the only use ?

Since this DAG combine doesn't look like an immediate win is it also worth explaining that we prefer to have this in a canonical form that can match existing isel patterns?

https://github.com/llvm/llvm-project/pull/118974