[llvm] [DAG] SimplifyDemandedBits - if we're just demanding a single shifted down sign bit, try to shift down the MSB directly (PR #114967)

[Simon Pilgrim via llvm-commits]

RKSimon wrote:

Yes at the moment its always the `(and (srl X, C), 1)` pattern AFAICT - if we're not going to try to extend this in the future then we can move it DAGCombine

https://github.com/llvm/llvm-project/pull/114967