[llvm] [DAG] SimplifyDemandedBits - if we're just demanding a single shifted down sign bit, try to shift down the MSB directly (PR #114967)

[Jay Foad via llvm-commits]

jayfoad wrote:

Does this only help when the result of the SRL is actually ANDed with 1, so changing it to SRL by 31 allows you to remove the AND? If so, could you implement this as a simplification of the AND instead of a demanded bits thing?

https://github.com/llvm/llvm-project/pull/114967