[llvm] [DAG] SimplifyDemandedBits - if we're just demanding a single shifted down sign bit, try to shift down the MSB directly (PR #114967)

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git-clang-format --diff 6d2f4dd79d0106b8f4c743b2fb08ae0ea29411e0 58cc3a4e7e2853b91a0c6fc75d8fc07b65af8c6a --extensions cpp -- llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp
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View the diff from clang-format here.
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diff --git a/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp b/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp
index 05b00ec1ff..4b9cc9d09f 100644
--- a/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp
@@ -1981,7 +1981,7 @@ bool TargetLowering::SimplifyDemandedBits(
       // If we are shifting down an extended sign bit, see if we can simplify
       // this to shifting the MSB directly to expose further simplifications.
       // This pattern often appears after sext_inreg legalization.
-      // 
+      //
       // NOTE: We might be able to generalize this and merge with the SRA fold
       // above, but there are currently regressions.
       if (DemandedBits == 1 && (BitWidth - 1) > ShAmt) {

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https://github.com/llvm/llvm-project/pull/114967