[llvm] [AMDGPU] Implement hasAndNot for scalar bitwise AND-NOT operations. (PR #112647)

[Matt Arsenault via llvm-commits]

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@@ -6043,3 +6043,11 @@ bool AMDGPUTargetLowering::isReassocProfitable(MachineRegisterInfo &MRI,
                                                Register N0, Register N1) const {
   return MRI.hasOneNonDBGUse(N0); // FIXME: handle regbanks
 }
+
+bool AMDGPUTargetLowering::hasAndNot(SDValue Op) const {
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arsenm wrote:

Should move this to SIISelLowering. Not sure if r600 has anything relevant 

https://github.com/llvm/llvm-project/pull/112647