[llvm] [AMDGPU] Implement hasAndNot for scalar bitwise AND-NOT operations. (PR #112647)
Harrison Hao via llvm-commits
llvm-commits at lists.llvm.org
Wed Oct 16 21:54:35 PDT 2024
https://github.com/harrisonGPU updated https://github.com/llvm/llvm-project/pull/112647
>From 1822dab3f3a4b3634bece0edd095c14b8f502a56 Mon Sep 17 00:00:00 2001
From: Harrison Hao <tsworld1314 at gmail.com>
Date: Thu, 17 Oct 2024 09:59:03 +0800
Subject: [PATCH 1/4] [AMDGPU] Implement hasAndNot for scalar bitwise AND-NOT
operations.
---
llvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp | 8 ++++++++
llvm/lib/Target/AMDGPU/AMDGPUISelLowering.h | 2 ++
2 files changed, 10 insertions(+)
diff --git a/llvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp b/llvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp
index 0f65df0763cc83..b746b94a60be21 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp
+++ b/llvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp
@@ -3721,6 +3721,14 @@ SDValue AMDGPUTargetLowering::LowerSIGN_EXTEND_INREG(SDValue Op,
return DAG.getBuildVector(VT, DL, Args);
}
+bool AMDGPUTargetLowering::hasAndNot(SDValue Op) const {
+ if (Op->isDivergent())
+ return false;
+
+ EVT VT = Op.getValueType();
+ return VT == MVT::i32 || VT == MVT::i64;
+}
+
//===----------------------------------------------------------------------===//
// Custom DAG optimizations
//===----------------------------------------------------------------------===//
diff --git a/llvm/lib/Target/AMDGPU/AMDGPUISelLowering.h b/llvm/lib/Target/AMDGPU/AMDGPUISelLowering.h
index b2fd31cb2346eb..1289458570358b 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPUISelLowering.h
+++ b/llvm/lib/Target/AMDGPU/AMDGPUISelLowering.h
@@ -99,6 +99,8 @@ class AMDGPUTargetLowering : public TargetLowering {
SDValue LowerSIGN_EXTEND_INREG(SDValue Op, SelectionDAG &DAG) const;
+ bool hasAndNot(SDValue Y) const override;
+
protected:
bool shouldCombineMemoryType(EVT VT) const;
SDValue performLoadCombine(SDNode *N, DAGCombinerInfo &DCI) const;
>From 43a26e7424299296ec1aaa1067d99a3185c4d294 Mon Sep 17 00:00:00 2001
From: Harrison Hao <tsworld1314 at gmail.com>
Date: Thu, 17 Oct 2024 10:31:26 +0800
Subject: [PATCH 2/4] [AMDGPU] Update value name.
---
llvm/lib/Target/AMDGPU/AMDGPUISelLowering.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/llvm/lib/Target/AMDGPU/AMDGPUISelLowering.h b/llvm/lib/Target/AMDGPU/AMDGPUISelLowering.h
index 1289458570358b..d05b8901c0cb6e 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPUISelLowering.h
+++ b/llvm/lib/Target/AMDGPU/AMDGPUISelLowering.h
@@ -99,7 +99,7 @@ class AMDGPUTargetLowering : public TargetLowering {
SDValue LowerSIGN_EXTEND_INREG(SDValue Op, SelectionDAG &DAG) const;
- bool hasAndNot(SDValue Y) const override;
+ bool hasAndNot(SDValue Op) const override;
protected:
bool shouldCombineMemoryType(EVT VT) const;
>From b873ad212233965cf7054fe13ca43696957cd2cb Mon Sep 17 00:00:00 2001
From: Harrison Hao <tsworld1314 at gmail.com>
Date: Thu, 17 Oct 2024 12:07:09 +0800
Subject: [PATCH 3/4] [AMDGPU] Update patch.
---
llvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp | 16 ++++++++--------
llvm/lib/Target/AMDGPU/AMDGPUISelLowering.h | 9 +++++++--
2 files changed, 15 insertions(+), 10 deletions(-)
diff --git a/llvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp b/llvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp
index b746b94a60be21..09860cfff96fc2 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp
+++ b/llvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp
@@ -3721,14 +3721,6 @@ SDValue AMDGPUTargetLowering::LowerSIGN_EXTEND_INREG(SDValue Op,
return DAG.getBuildVector(VT, DL, Args);
}
-bool AMDGPUTargetLowering::hasAndNot(SDValue Op) const {
- if (Op->isDivergent())
- return false;
-
- EVT VT = Op.getValueType();
- return VT == MVT::i32 || VT == MVT::i64;
-}
-
//===----------------------------------------------------------------------===//
// Custom DAG optimizations
//===----------------------------------------------------------------------===//
@@ -6051,3 +6043,11 @@ bool AMDGPUTargetLowering::isReassocProfitable(MachineRegisterInfo &MRI,
Register N0, Register N1) const {
return MRI.hasOneNonDBGUse(N0); // FIXME: handle regbanks
}
+
+bool AMDGPUTargetLowering::hasAndNot(SDValue Op) const {
+ if (Op->isDivergent())
+ return false;
+
+ EVT VT = Op.getValueType();
+ return VT == MVT::i32 || VT == MVT::i64;
+}
diff --git a/llvm/lib/Target/AMDGPU/AMDGPUISelLowering.h b/llvm/lib/Target/AMDGPU/AMDGPUISelLowering.h
index d05b8901c0cb6e..952c95eba63760 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPUISelLowering.h
+++ b/llvm/lib/Target/AMDGPU/AMDGPUISelLowering.h
@@ -99,8 +99,6 @@ class AMDGPUTargetLowering : public TargetLowering {
SDValue LowerSIGN_EXTEND_INREG(SDValue Op, SelectionDAG &DAG) const;
- bool hasAndNot(SDValue Op) const override;
-
protected:
bool shouldCombineMemoryType(EVT VT) const;
SDValue performLoadCombine(SDNode *N, DAGCombinerInfo &DCI) const;
@@ -389,6 +387,13 @@ class AMDGPUTargetLowering : public TargetLowering {
MVT getFenceOperandTy(const DataLayout &DL) const override {
return MVT::i32;
}
+
+ /// Return true if the target supports a bitwise and-not operation:
+ /// X = ~A & B
+ /// This function checks if the operation can be directly mapped to the
+ /// target's native instructions, potentially simplifying select or other
+ /// related instructions by using more efficient hardware-specific operations.
+ bool hasAndNot(SDValue Op) const override;
};
namespace AMDGPUISD {
>From e75dde769d705388720e6d967d51ed319d87cc13 Mon Sep 17 00:00:00 2001
From: Harrison Hao <tsworld1314 at gmail.com>
Date: Thu, 17 Oct 2024 12:54:13 +0800
Subject: [PATCH 4/4] [AMDGPU] Move to SIISelLowering.
---
llvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp | 8 --------
llvm/lib/Target/AMDGPU/AMDGPUISelLowering.h | 7 -------
llvm/lib/Target/AMDGPU/SIISelLowering.cpp | 8 ++++++++
llvm/lib/Target/AMDGPU/SIISelLowering.h | 7 +++++++
4 files changed, 15 insertions(+), 15 deletions(-)
diff --git a/llvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp b/llvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp
index 09860cfff96fc2..0f65df0763cc83 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp
+++ b/llvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp
@@ -6043,11 +6043,3 @@ bool AMDGPUTargetLowering::isReassocProfitable(MachineRegisterInfo &MRI,
Register N0, Register N1) const {
return MRI.hasOneNonDBGUse(N0); // FIXME: handle regbanks
}
-
-bool AMDGPUTargetLowering::hasAndNot(SDValue Op) const {
- if (Op->isDivergent())
- return false;
-
- EVT VT = Op.getValueType();
- return VT == MVT::i32 || VT == MVT::i64;
-}
diff --git a/llvm/lib/Target/AMDGPU/AMDGPUISelLowering.h b/llvm/lib/Target/AMDGPU/AMDGPUISelLowering.h
index 952c95eba63760..b2fd31cb2346eb 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPUISelLowering.h
+++ b/llvm/lib/Target/AMDGPU/AMDGPUISelLowering.h
@@ -387,13 +387,6 @@ class AMDGPUTargetLowering : public TargetLowering {
MVT getFenceOperandTy(const DataLayout &DL) const override {
return MVT::i32;
}
-
- /// Return true if the target supports a bitwise and-not operation:
- /// X = ~A & B
- /// This function checks if the operation can be directly mapped to the
- /// target's native instructions, potentially simplifying select or other
- /// related instructions by using more efficient hardware-specific operations.
- bool hasAndNot(SDValue Op) const override;
};
namespace AMDGPUISD {
diff --git a/llvm/lib/Target/AMDGPU/SIISelLowering.cpp b/llvm/lib/Target/AMDGPU/SIISelLowering.cpp
index de9173e923ab5c..f59f25c7117491 100644
--- a/llvm/lib/Target/AMDGPU/SIISelLowering.cpp
+++ b/llvm/lib/Target/AMDGPU/SIISelLowering.cpp
@@ -16890,3 +16890,11 @@ SITargetLowering::lowerIdempotentRMWIntoFencedLoad(AtomicRMWInst *AI) const {
AI->eraseFromParent();
return LI;
}
+
+bool SITargetLowering::hasAndNot(SDValue Op) const {
+ if (Op->isDivergent())
+ return false;
+
+ EVT VT = Op.getValueType();
+ return VT == MVT::i32 || VT == MVT::i64;
+}
diff --git a/llvm/lib/Target/AMDGPU/SIISelLowering.h b/llvm/lib/Target/AMDGPU/SIISelLowering.h
index 6c3edf37945e24..b2094ad7993316 100644
--- a/llvm/lib/Target/AMDGPU/SIISelLowering.h
+++ b/llvm/lib/Target/AMDGPU/SIISelLowering.h
@@ -598,6 +598,13 @@ class SITargetLowering final : public AMDGPUTargetLowering {
MachineMemOperand::Flags
getTargetMMOFlags(const Instruction &I) const override;
+
+ /// Return true if the target supports a bitwise and-not operation:
+ /// X = ~A & B
+ /// This function checks if the operation can be directly mapped to the
+ /// target's native instructions, potentially simplifying select or other
+ /// related instructions by using more efficient hardware-specific operations.
+ bool hasAndNot(SDValue Op) const override;
};
// Returns true if argument is a boolean value which is not serialized into
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