[llvm] [RISCV] Handle undef passthrus in foldVMV_V_V (PR #106943)

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llvmbot wrote:


<!--LLVM PR SUMMARY COMMENT-->

@llvm/pr-subscribers-backend-risc-v

Author: Luke Lau (lukel97)

<details>
<summary>Changes</summary>

If a PseudoVMV_V_V's passthru is undef then we don't need the Src to have the same passthru, nor do we need to check its VL.

The tail policy in these tests is still tu, #<!-- -->105788 should fix this separately.


---
Full diff: https://github.com/llvm/llvm-project/pull/106943.diff


3 Files Affected:

- (modified) llvm/lib/Target/RISCV/RISCVVectorPeephole.cpp (+23-21) 
- (modified) llvm/test/CodeGen/RISCV/rvv/vmv.v.v-peephole.ll (+11) 
- (modified) llvm/test/CodeGen/RISCV/rvv/vmv.v.v-peephole.mir (+14) 


``````````diff
diff --git a/llvm/lib/Target/RISCV/RISCVVectorPeephole.cpp b/llvm/lib/Target/RISCV/RISCVVectorPeephole.cpp
index 412fd790061a37..c885b6bc2e50d4 100644
--- a/llvm/lib/Target/RISCV/RISCVVectorPeephole.cpp
+++ b/llvm/lib/Target/RISCV/RISCVVectorPeephole.cpp
@@ -503,30 +503,32 @@ bool RISCVVectorPeephole::foldVMV_V_V(MachineInstr &MI) {
   if (getSEWLMULRatio(MI) != getSEWLMULRatio(*Src))
     return false;
 
-  // Src needs to have the same passthru as VMV_V_V
-  MachineOperand &SrcPassthru = Src->getOperand(1);
-  if (SrcPassthru.getReg() != RISCV::NoRegister &&
-      SrcPassthru.getReg() != Passthru.getReg())
-    return false;
+  if (Passthru.getReg() != RISCV::NoRegister) {
+    // Src needs to have the same passthru as VMV_V_V
+    MachineOperand &SrcPassthru = Src->getOperand(1);
+    if (SrcPassthru.getReg() != RISCV::NoRegister &&
+	SrcPassthru.getReg() != Passthru.getReg())
+      return false;
 
-  // Src VL will have already been reduced if legal (see tryToReduceVL),
-  // so we don't need to handle a smaller source VL here.  However, the
-  // user's VL may be larger
-  MachineOperand &SrcVL = Src->getOperand(RISCVII::getVLOpNum(Src->getDesc()));
-  if (!isVLKnownLE(SrcVL, MI.getOperand(3)))
-    return false;
+    // Src VL will have already been reduced if legal (see tryToReduceVL),
+    // so we don't need to handle a smaller source VL here.  However, the
+    // user's VL may be larger
+    MachineOperand &SrcVL = Src->getOperand(RISCVII::getVLOpNum(Src->getDesc()));
+    if (!isVLKnownLE(SrcVL, MI.getOperand(3)))
+      return false;
 
-  // If the new passthru doesn't dominate Src, try to move Src so it does.
-  if (!ensureDominates(Passthru, *Src))
-    return false;
+    // If the new passthru doesn't dominate Src, try to move Src so it does.
+    if (!ensureDominates(Passthru, *Src))
+      return false;
 
-  if (SrcPassthru.getReg() != Passthru.getReg()) {
-    SrcPassthru.setReg(Passthru.getReg());
-    // If Src is masked then its passthru needs to be in VRNoV0.
-    if (Passthru.getReg() != RISCV::NoRegister)
-      MRI->constrainRegClass(Passthru.getReg(),
-                             TII->getRegClass(Src->getDesc(), 1, TRI,
-                                              *Src->getParent()->getParent()));
+    if (SrcPassthru.getReg() != Passthru.getReg()) {
+      SrcPassthru.setReg(Passthru.getReg());
+      // If Src is masked then its passthru needs to be in VRNoV0.
+      if (Passthru.getReg() != RISCV::NoRegister)
+	MRI->constrainRegClass(Passthru.getReg(),
+                               TII->getRegClass(Src->getDesc(), 1, TRI,
+						*Src->getParent()->getParent()));
+    }
   }
 
   // Use a conservative tu,mu policy, RISCVInsertVSETVLI will relax it if
diff --git a/llvm/test/CodeGen/RISCV/rvv/vmv.v.v-peephole.ll b/llvm/test/CodeGen/RISCV/rvv/vmv.v.v-peephole.ll
index 3952e48c5c28fc..252ddb267a5ad2 100644
--- a/llvm/test/CodeGen/RISCV/rvv/vmv.v.v-peephole.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/vmv.v.v-peephole.ll
@@ -194,3 +194,14 @@ define <vscale x 2 x i32> @unfoldable_mismatched_sew(<vscale x 2 x i32> %passthr
   %b = call <vscale x 2 x i32> @llvm.riscv.vmv.v.v.nxv2i32(<vscale x 2 x i32> %passthru, <vscale x 2 x i32> %a.bitcast, iXLen %avl)
   ret <vscale x 2 x i32> %b
 }
+
+define <vscale x 1 x i64> @undef_passthru(<vscale x 1 x i64> %passthru, <vscale x 1 x i64> %x, <vscale x 1 x i64> %y, iXLen %avl) {
+; CHECK-LABEL: undef_passthru:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli zero, a0, e64, m1, tu, ma
+; CHECK-NEXT:    vadd.vv v8, v9, v10
+; CHECK-NEXT:    ret
+  %a = call <vscale x 1 x i64> @llvm.riscv.vadd.nxv1i64.nxv1i64(<vscale x 1 x i64> %passthru, <vscale x 1 x i64> %x, <vscale x 1 x i64> %y, iXLen %avl)
+  %b = call <vscale x 1 x i64> @llvm.riscv.vmv.v.v.nxv1i64(<vscale x 1 x i64> undef, <vscale x 1 x i64> %a, iXLen %avl)
+  ret <vscale x 1 x i64> %b
+}
diff --git a/llvm/test/CodeGen/RISCV/rvv/vmv.v.v-peephole.mir b/llvm/test/CodeGen/RISCV/rvv/vmv.v.v-peephole.mir
index b2526c6df6939e..3672424438234e 100644
--- a/llvm/test/CodeGen/RISCV/rvv/vmv.v.v-peephole.mir
+++ b/llvm/test/CodeGen/RISCV/rvv/vmv.v.v-peephole.mir
@@ -18,3 +18,17 @@ body: |
     %y:gpr = ADDI $x0, 1
     %z:vr = PseudoVMV_V_V_M1 %passthru, %x, 4, 5 /* e32 */, 0 /* tu, mu */
 ...
+---
+name: undef_passthru
+body: |
+  bb.0:
+    liveins: $v8
+    ; CHECK-LABEL: name: undef_passthru
+    ; CHECK: liveins: $v8
+    ; CHECK-NEXT: {{  $}}
+    ; CHECK-NEXT: %passthru:vr = COPY $v8
+    ; CHECK-NEXT: %x:vr = PseudoVADD_VV_M1 %passthru, $noreg, $noreg, 4, 5 /* e32 */, 0 /* tu, mu */
+    %passthru:vr = COPY $v8
+    %x:vr = PseudoVADD_VV_M1 %passthru, $noreg, $noreg, 4, 5 /* e32 */, 0 /* tu, mu */
+    %y:vr = PseudoVMV_V_V_M1 $noreg, %x, 4, 5 /* e32 */, 1 /* ta, mu */
+...

``````````

</details>


https://github.com/llvm/llvm-project/pull/106943