[llvm] [RISCV] Handle undef passthrus in foldVMV_V_V (PR #106943)
Luke Lau via llvm-commits
llvm-commits at lists.llvm.org
Mon Sep 2 00:12:24 PDT 2024
https://github.com/lukel97 created https://github.com/llvm/llvm-project/pull/106943
If a PseudoVMV_V_V's passthru is undef then we don't need the Src to have the same passthru, nor do we need to check its VL.
The tail policy in these tests is still tu, #105788 should fix this separately.
>From f4adb1dac443888f18f2d58a813ec8742ea38e83 Mon Sep 17 00:00:00 2001
From: Luke Lau <luke at igalia.com>
Date: Fri, 23 Aug 2024 14:27:12 +0800
Subject: [PATCH 1/2] Precommit tests
---
llvm/test/CodeGen/RISCV/rvv/vmv.v.v-peephole.ll | 13 +++++++++++++
llvm/test/CodeGen/RISCV/rvv/vmv.v.v-peephole.mir | 15 +++++++++++++++
2 files changed, 28 insertions(+)
diff --git a/llvm/test/CodeGen/RISCV/rvv/vmv.v.v-peephole.ll b/llvm/test/CodeGen/RISCV/rvv/vmv.v.v-peephole.ll
index 3952e48c5c28fc..fd7d791903d0f2 100644
--- a/llvm/test/CodeGen/RISCV/rvv/vmv.v.v-peephole.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/vmv.v.v-peephole.ll
@@ -194,3 +194,16 @@ define <vscale x 2 x i32> @unfoldable_mismatched_sew(<vscale x 2 x i32> %passthr
%b = call <vscale x 2 x i32> @llvm.riscv.vmv.v.v.nxv2i32(<vscale x 2 x i32> %passthru, <vscale x 2 x i32> %a.bitcast, iXLen %avl)
ret <vscale x 2 x i32> %b
}
+
+define <vscale x 1 x i64> @undef_passthru(<vscale x 1 x i64> %passthru, <vscale x 1 x i64> %x, <vscale x 1 x i64> %y, iXLen %avl) {
+; CHECK-LABEL: undef_passthru:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli zero, a0, e64, m1, tu, ma
+; CHECK-NEXT: vadd.vv v8, v9, v10
+; CHECK-NEXT: vsetvli zero, zero, e64, m1, ta, ma
+; CHECK-NEXT: vmv.v.v v8, v8
+; CHECK-NEXT: ret
+ %a = call <vscale x 1 x i64> @llvm.riscv.vadd.nxv1i64.nxv1i64(<vscale x 1 x i64> %passthru, <vscale x 1 x i64> %x, <vscale x 1 x i64> %y, iXLen %avl)
+ %b = call <vscale x 1 x i64> @llvm.riscv.vmv.v.v.nxv1i64(<vscale x 1 x i64> undef, <vscale x 1 x i64> %a, iXLen %avl)
+ ret <vscale x 1 x i64> %b
+}
diff --git a/llvm/test/CodeGen/RISCV/rvv/vmv.v.v-peephole.mir b/llvm/test/CodeGen/RISCV/rvv/vmv.v.v-peephole.mir
index b2526c6df6939e..2dd937b103bfc0 100644
--- a/llvm/test/CodeGen/RISCV/rvv/vmv.v.v-peephole.mir
+++ b/llvm/test/CodeGen/RISCV/rvv/vmv.v.v-peephole.mir
@@ -18,3 +18,18 @@ body: |
%y:gpr = ADDI $x0, 1
%z:vr = PseudoVMV_V_V_M1 %passthru, %x, 4, 5 /* e32 */, 0 /* tu, mu */
...
+---
+name: undef_passthru
+body: |
+ bb.0:
+ liveins: $v8
+ ; CHECK-LABEL: name: undef_passthru
+ ; CHECK: liveins: $v8
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: %passthru:vr = COPY $v8
+ ; CHECK-NEXT: %x:vr = PseudoVADD_VV_M1 %passthru, $noreg, $noreg, 4, 5 /* e32 */, 0 /* tu, mu */
+ ; CHECK-NEXT: %y:vr = PseudoVMV_V_V_M1 $noreg, %x, 4, 5 /* e32 */, 1 /* ta, mu */
+ %passthru:vr = COPY $v8
+ %x:vr = PseudoVADD_VV_M1 %passthru, $noreg, $noreg, 4, 5 /* e32 */, 0 /* tu, mu */
+ %y:vr = PseudoVMV_V_V_M1 $noreg, %x, 4, 5 /* e32 */, 1 /* ta, mu */
+...
>From 11f6caedaf9570a78503d4cea340c1e12990855b Mon Sep 17 00:00:00 2001
From: Luke Lau <luke at igalia.com>
Date: Mon, 2 Sep 2024 14:49:09 +0800
Subject: [PATCH 2/2] [RISCV] Handle undef passthrus in foldVMV_V_V
If a PseudoVMV_V_V's passthru is undef then we don't need the Src to have the same passthru, nor do we need to check its VL.
The tail policy in these tests is still tu, #105788 should fix this separately.
---
llvm/lib/Target/RISCV/RISCVVectorPeephole.cpp | 44 ++++++++++---------
.../CodeGen/RISCV/rvv/vmv.v.v-peephole.ll | 2 -
.../CodeGen/RISCV/rvv/vmv.v.v-peephole.mir | 1 -
3 files changed, 23 insertions(+), 24 deletions(-)
diff --git a/llvm/lib/Target/RISCV/RISCVVectorPeephole.cpp b/llvm/lib/Target/RISCV/RISCVVectorPeephole.cpp
index 412fd790061a37..c885b6bc2e50d4 100644
--- a/llvm/lib/Target/RISCV/RISCVVectorPeephole.cpp
+++ b/llvm/lib/Target/RISCV/RISCVVectorPeephole.cpp
@@ -503,30 +503,32 @@ bool RISCVVectorPeephole::foldVMV_V_V(MachineInstr &MI) {
if (getSEWLMULRatio(MI) != getSEWLMULRatio(*Src))
return false;
- // Src needs to have the same passthru as VMV_V_V
- MachineOperand &SrcPassthru = Src->getOperand(1);
- if (SrcPassthru.getReg() != RISCV::NoRegister &&
- SrcPassthru.getReg() != Passthru.getReg())
- return false;
+ if (Passthru.getReg() != RISCV::NoRegister) {
+ // Src needs to have the same passthru as VMV_V_V
+ MachineOperand &SrcPassthru = Src->getOperand(1);
+ if (SrcPassthru.getReg() != RISCV::NoRegister &&
+ SrcPassthru.getReg() != Passthru.getReg())
+ return false;
- // Src VL will have already been reduced if legal (see tryToReduceVL),
- // so we don't need to handle a smaller source VL here. However, the
- // user's VL may be larger
- MachineOperand &SrcVL = Src->getOperand(RISCVII::getVLOpNum(Src->getDesc()));
- if (!isVLKnownLE(SrcVL, MI.getOperand(3)))
- return false;
+ // Src VL will have already been reduced if legal (see tryToReduceVL),
+ // so we don't need to handle a smaller source VL here. However, the
+ // user's VL may be larger
+ MachineOperand &SrcVL = Src->getOperand(RISCVII::getVLOpNum(Src->getDesc()));
+ if (!isVLKnownLE(SrcVL, MI.getOperand(3)))
+ return false;
- // If the new passthru doesn't dominate Src, try to move Src so it does.
- if (!ensureDominates(Passthru, *Src))
- return false;
+ // If the new passthru doesn't dominate Src, try to move Src so it does.
+ if (!ensureDominates(Passthru, *Src))
+ return false;
- if (SrcPassthru.getReg() != Passthru.getReg()) {
- SrcPassthru.setReg(Passthru.getReg());
- // If Src is masked then its passthru needs to be in VRNoV0.
- if (Passthru.getReg() != RISCV::NoRegister)
- MRI->constrainRegClass(Passthru.getReg(),
- TII->getRegClass(Src->getDesc(), 1, TRI,
- *Src->getParent()->getParent()));
+ if (SrcPassthru.getReg() != Passthru.getReg()) {
+ SrcPassthru.setReg(Passthru.getReg());
+ // If Src is masked then its passthru needs to be in VRNoV0.
+ if (Passthru.getReg() != RISCV::NoRegister)
+ MRI->constrainRegClass(Passthru.getReg(),
+ TII->getRegClass(Src->getDesc(), 1, TRI,
+ *Src->getParent()->getParent()));
+ }
}
// Use a conservative tu,mu policy, RISCVInsertVSETVLI will relax it if
diff --git a/llvm/test/CodeGen/RISCV/rvv/vmv.v.v-peephole.ll b/llvm/test/CodeGen/RISCV/rvv/vmv.v.v-peephole.ll
index fd7d791903d0f2..252ddb267a5ad2 100644
--- a/llvm/test/CodeGen/RISCV/rvv/vmv.v.v-peephole.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/vmv.v.v-peephole.ll
@@ -200,8 +200,6 @@ define <vscale x 1 x i64> @undef_passthru(<vscale x 1 x i64> %passthru, <vscale
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli zero, a0, e64, m1, tu, ma
; CHECK-NEXT: vadd.vv v8, v9, v10
-; CHECK-NEXT: vsetvli zero, zero, e64, m1, ta, ma
-; CHECK-NEXT: vmv.v.v v8, v8
; CHECK-NEXT: ret
%a = call <vscale x 1 x i64> @llvm.riscv.vadd.nxv1i64.nxv1i64(<vscale x 1 x i64> %passthru, <vscale x 1 x i64> %x, <vscale x 1 x i64> %y, iXLen %avl)
%b = call <vscale x 1 x i64> @llvm.riscv.vmv.v.v.nxv1i64(<vscale x 1 x i64> undef, <vscale x 1 x i64> %a, iXLen %avl)
diff --git a/llvm/test/CodeGen/RISCV/rvv/vmv.v.v-peephole.mir b/llvm/test/CodeGen/RISCV/rvv/vmv.v.v-peephole.mir
index 2dd937b103bfc0..3672424438234e 100644
--- a/llvm/test/CodeGen/RISCV/rvv/vmv.v.v-peephole.mir
+++ b/llvm/test/CodeGen/RISCV/rvv/vmv.v.v-peephole.mir
@@ -28,7 +28,6 @@ body: |
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: %passthru:vr = COPY $v8
; CHECK-NEXT: %x:vr = PseudoVADD_VV_M1 %passthru, $noreg, $noreg, 4, 5 /* e32 */, 0 /* tu, mu */
- ; CHECK-NEXT: %y:vr = PseudoVMV_V_V_M1 $noreg, %x, 4, 5 /* e32 */, 1 /* ta, mu */
%passthru:vr = COPY $v8
%x:vr = PseudoVADD_VV_M1 %passthru, $noreg, $noreg, 4, 5 /* e32 */, 0 /* tu, mu */
%y:vr = PseudoVMV_V_V_M1 $noreg, %x, 4, 5 /* e32 */, 1 /* ta, mu */
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