[clang] [llvm] [RISCV] Add Syntacore SCR4 RV32/64 processors definition (PR #101321)

[Anton Sidorenko via llvm-commits]

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@@ -106,6 +106,7 @@ Changes to the RISC-V Backend
 * `.balign N, 0`, `.p2align N, 0`, `.align N, 0` in code sections will now fill
   the required alignment space with a sequence of `0x0` bytes (the requested
   fill value) rather than NOPs.
+* Added Syntacore SCR4 CPUs: ``-mcpu=syntacore-scr4-rv32/64``
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asi-sc wrote:

Hm, actually not sure. It looks like a change to RISC-V backend (which is propagated to the driver) and previously we mentioned such changes in llvm release notes e.g. https://github.com/llvm/llvm-project/blob/release/18.x/llvm/docs/ReleaseNotes.rst#changes-to-the-risc-v-backend or https://github.com/llvm/llvm-project/blob/release/19.x/llvm/docs/ReleaseNotes.rst#changes-to-the-risc-v-backend .  Although I don't have a strong opinion on this matter.

https://github.com/llvm/llvm-project/pull/101321